Cirrus-logic EP93xx Uživatelský manuál

©Copyright 2007 Cirrus Logic, Inc. SEP 2007DS785UM1http://www.cirrus.comEP93XX ARM®9 Embedded Processor FamilyEP93xx User’s Guide

x ©Copyright 2007 Cirrus Logic, Inc. DS785UM1 EP93xx User’s Guide 14.2.1.9 Interrupt Generation Logic ...

3-30 DS785UM1Copyright 2007 Cirrus Logic MaverickCrunch Co-ProcessorEP93xx User’s Guide333Move 64-bit Integer from AccumulatorDescription:Saturates an

DS785UM1 3-31Copyright 2007 Cirrus Logic MaverickCrunch Co-ProcessorEP93xx User’s Guide333Move from Control/Status Register to MaverickCrunch Register

3-32 DS785UM1Copyright 2007 Cirrus Logic MaverickCrunch Co-ProcessorEP93xx User’s Guide333Convert Single Precision Floating Point to Double Precision

DS785UM1 3-33Copyright 2007 Cirrus Logic MaverickCrunch Co-ProcessorEP93xx User’s Guide333Convert 32-bit Integer to Double Precision Floating PointDes

3-34 DS785UM1Copyright 2007 Cirrus Logic MaverickCrunch Co-ProcessorEP93xx User’s Guide333Convert Single Precision Floating Point to 32-bit IntegerDes

DS785UM1 3-35Copyright 2007 Cirrus Logic MaverickCrunch Co-ProcessorEP93xx User’s Guide333Bit Definitions:CRd: Destination register CRn: Source regist

3-36 DS785UM1Copyright 2007 Cirrus Logic MaverickCrunch Co-ProcessorEP93xx User’s Guide333Shift 32-bit Integer ImmediateDefinition:Shift a 32-bit inte

DS785UM1 3-37Copyright 2007 Cirrus Logic MaverickCrunch Co-ProcessorEP93xx User’s Guide333Mnemonic:CFCMPS<cond> Rd, CRn, CRmBit Definitions:CRn:

3-38 DS785UM1Copyright 2007 Cirrus Logic MaverickCrunch Co-ProcessorEP93xx User’s Guide333Rd: Destination ARM register. If Rd = 15, destination is AR

DS785UM1 3-39Copyright 2007 Cirrus Logic MaverickCrunch Co-ProcessorEP93xx User’s Guide333Bit Definitions:CRd: Destination register CRn: Source regist

DS785UM1 ©Copyright 2007 Cirrus Logic, Inc. xiEP93xx User’s GuideChapter 17. IrDA ...

3-40 DS785UM1Copyright 2007 Cirrus Logic MaverickCrunch Co-ProcessorEP93xx User’s Guide333Double Precision Floating Point AddDescription:Adds two doub

DS785UM1 3-41Copyright 2007 Cirrus Logic MaverickCrunch Co-ProcessorEP93xx User’s Guide333Single Precision Floating Point MultiplyDescription:Multipli

3-42 DS785UM1Copyright 2007 Cirrus Logic MaverickCrunch Co-ProcessorEP93xx User’s Guide33364-bit Integer Absolute ValueDescription:Computes the absolu

DS785UM1 3-43Copyright 2007 Cirrus Logic MaverickCrunch Co-ProcessorEP93xx User’s Guide333Mnemonic:CFADD32<cond> CRd, CRn, CRmBit Definitions:CR

3-44 DS785UM1Copyright 2007 Cirrus Logic MaverickCrunch Co-ProcessorEP93xx User’s Guide333Bit Definitions:CRd: Destination register CRn: Minuend regis

DS785UM1 3-45Copyright 2007 Cirrus Logic MaverickCrunch Co-ProcessorEP93xx User’s Guide333Bit Definitions:CRd: Destination/addend register CRn: Multip

3-46 DS785UM1Copyright 2007 Cirrus Logic MaverickCrunch Co-ProcessorEP93xx User’s Guide33332-bit Integer Multiply-Subtract, Result to AccumulatorDescr

DS785UM1 3-47Copyright 2007 Cirrus Logic MaverickCrunch Co-ProcessorEP93xx User’s Guide33332-bit Integer Multiply-Subtract from AccumulatorDescription

3-48 DS785UM1Copyright 2007 Cirrus Logic MaverickCrunch Co-ProcessorEP93xx User’s Guide333

DS785UM1 4-1Copyright 2007 Cirrus Logic 444Chapter 44Boot ROM 4.1 IntroductionThe Boot ROM allows a program or OS to boot from the following devices:

xii ©Copyright 2007 Cirrus Logic, Inc. DS785UM1 EP93xx User’s GuideChapter 20. Real Time Clock With Software Trim ...

4-2 DS785UM1Copyright 2007 Cirrus LogicBoot ROMEP93xx User’s Guide444Note that the code retrieved via UART1 and the SPI Serial Flash is not intended t

DS785UM1 4-3Copyright 2007 Cirrus Logic Boot ROMEP93xx User’s Guide4448. If it is not a Serial Download, attempt to read from SPI Serial Flash (see Fi

4-4 DS785UM1Copyright 2007 Cirrus LogicBoot ROMEP93xx User’s Guide444 Figure 4-1. Flow Chart of Boot ROM Software 4.2 Boot OptionsTable 4-1 show

DS785UM1 4-5Copyright 2007 Cirrus Logic Boot ROMEP93xx User’s Guide444Note: ASYNC boot mode is the preferred boot mode type for new designs.Table 4-1.

4-6 DS785UM1Copyright 2007 Cirrus LogicBoot ROMEP93xx User’s Guide444 4.2.1 UART BootMake sure that the boot configuration pins (see Table 5-1 on pag

DS785UM1 4-7Copyright 2007 Cirrus Logic Boot ROMEP93xx User’s Guide4440x3000_10000x6000_00000x7000_0000Code execution will start at address FLASH base

4-8 DS785UM1Copyright 2007 Cirrus LogicBoot ROMEP93xx User’s Guide4443. Run the internal boot code and boot from FLASH4. Set the PLL back to use the e

DS785UM1 5-1Copyright 2007 Cirrus Logic 555Chapter 55System Controller 5.1 IntroductionThe System Controller (Syscon) provides:• Clock control• Power

5-2 DS785UM1Copyright 2007 Cirrus LogicSystem ControllerEP93xx User’s Guide555certain system variables such as RTC, SDRAM refresh control/global confi

DS785UM1 5-3Copyright 2007 Cirrus Logic System ControllerEP93xx User’s Guide555The normal boot function is described in Chapter 4 on page 4-1.Serial b

DS785UM1 ©Copyright 2007 Cirrus Logic, Inc. xiiiEP93xx User’s Guide 23.5 Configuring the SSP . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5-4 DS785UM1Copyright 2007 Cirrus LogicSystem ControllerEP93xx User’s Guide555Note: ASYNC boot mode is the preferred boot mode type for new designs.

DS785UM1 5-5Copyright 2007 Cirrus Logic System ControllerEP93xx User’s Guide555Both PLLs are software programmable (each value is defined in “ClkSet1”

5-6 DS785UM1Copyright 2007 Cirrus LogicSystem ControllerEP93xx User’s Guide555 Figure 5-2. Clock Generation System 5.1.5.2.1 Bus Clock GenerationFigu

DS785UM1 5-7Copyright 2007 Cirrus Logic System ControllerEP93xx User’s Guide555 Figure 5-3. Bus Clock GenerationThere are some limitations of each cl

5-8 DS785UM1Copyright 2007 Cirrus LogicSystem ControllerEP93xx User’s Guide555Even though FCLK is the usual CPU clock, HCLK can optionally be used ins

DS785UM1 5-9Copyright 2007 Cirrus Logic System ControllerEP93xx User’s Guide555 5.1.5.3 Steps for Clock ConfigurationThe boot ROM must contain code th

5-10 DS785UM1Copyright 2007 Cirrus LogicSystem ControllerEP93xx User’s Guide555 HCLK to the USB Hosts can be gated off as well to further save power.

DS785UM1 5-11Copyright 2007 Cirrus Logic System ControllerEP93xx User’s Guide555 Figure 5-4. Power States and Transitions 5.1.6.2.1 Power-on-Reset

5-12 DS785UM1Copyright 2007 Cirrus LogicSystem ControllerEP93xx User’s Guide555set. One example of this is when a power-on-reset is applied and this r

DS785UM1 5-13Copyright 2007 Cirrus Logic System ControllerEP93xx User’s Guide555 5.2 RegistersThis section contains the detailed register description

xiv ©Copyright 2007 Cirrus Logic, Inc. DS785UM1 EP93xx User’s GuideChapter 27. IDE Interface...

5-14 DS785UM1Copyright 2007 Cirrus LogicSystem ControllerEP93xx User’s Guide555Register DescriptionsPwrSts Address:0x8093_0000 - Read OnlyDefinition

DS785UM1 5-15Copyright 2007 Cirrus Logic System ControllerEP93xx User’s Guide555RSTFLG: Reset flag. This bit is set if the user reset button has beenp

5-16 DS785UM1Copyright 2007 Cirrus LogicSystem ControllerEP93xx User’s Guide555DMA M2M/P CHx: These bits enable the clocks to the DMA controllerchanne

DS785UM1 5-17Copyright 2007 Cirrus Logic System ControllerEP93xx User’s Guide555Standby and Halt Address:Standby - 0x8093_000C - Read OnlyHalt - 0x8

5-18 DS785UM1Copyright 2007 Cirrus LogicSystem ControllerEP93xx User’s Guide555STFClr Address:0x8093_001C - WriteDefinition:Writing to the STFClr loca

DS785UM1 5-19Copyright 2007 Cirrus Logic System ControllerEP93xx User’s Guide555PLL1_X2FBD2: These 6 register bits set the first feedback divider bits

5-20 DS785UM1Copyright 2007 Cirrus LogicSystem ControllerEP93xx User’s Guide555nBYP1: This bit selects the clock source for the processor clockdivide

DS785UM1 5-21Copyright 2007 Cirrus Logic System ControllerEP93xx User’s Guide555PLL2_X2FBD2: These 6 register bits set the first feedback divider bits

5-22 DS785UM1Copyright 2007 Cirrus LogicSystem ControllerEP93xx User’s Guide555ScratchReg0, ScratchReg1 Address:ScratchReg0 - 0x8093_0040, Read/Writ

DS785UM1 5-23Copyright 2007 Cirrus Logic System ControllerEP93xx User’s Guide555BusMstrArb Address:0x8093_0054 - Read/WriteDefinition:The Bus Master a

DS785UM1 ©Copyright 2007 Cirrus Logic, Inc. xvEP93xx User’s Guide Figure 4-1. Flow Chart of Boot ROM Software...

5-24 DS785UM1Copyright 2007 Cirrus LogicSystem ControllerEP93xx User’s Guide555DMA_ENFIQ: When set the arbiter will degrant DMA from the AHB busand wi

DS785UM1 5-25Copyright 2007 Cirrus Logic System ControllerEP93xx User’s Guide555DeviceCfg Address:0x8093_0080 - Read/Write, Software lockedDefault:0

5-26 DS785UM1Copyright 2007 Cirrus LogicSystem ControllerEP93xx User’s Guide555I2SonAC97: Audio - I2S on AC97 pins. The I2S block uses the AC97pins. S

DS785UM1 5-27Copyright 2007 Cirrus Logic System ControllerEP93xx User’s Guide5550 - GPIO Port H used for IDE1 - GPIO Port H used for GPIOHC3IN: HDLC3

5-28 DS785UM1Copyright 2007 Cirrus LogicSystem ControllerEP93xx User’s Guide555A1onG: I2S Audio Port 1 on GPIO. 1 - I2S Port 1 pins are mapped to EGPI

DS785UM1 5-29Copyright 2007 Cirrus Logic System ControllerEP93xx User’s Guide555SWRST: Software reset. A one to zero transition of this bit initiatesa

5-30 DS785UM1Copyright 2007 Cirrus LogicSystem ControllerEP93xx User’s Guide555MIRClkDiv Address:0x8093_0088 - Read/Write, Software lockedDefault:0x

DS785UM1 5-31Copyright 2007 Cirrus Logic System ControllerEP93xx User’s Guide555I2SClkDiv Address:0x8093_008C - Read/Write, Software lockedDefault:0

5-32 DS785UM1Copyright 2007 Cirrus LogicSystem ControllerEP93xx User’s Guide555SDIV: SCLK divide select. 1 - SCLK = MCLK / 4, 0 - SCLK = MCLK / 2.MENA

DS785UM1 5-33Copyright 2007 Cirrus Logic System ControllerEP93xx User’s Guide555ADIV: ADC clock divider value. 0 - ADC Clock is divide-by-16 from the

xvi ©Copyright 2007 Cirrus Logic, Inc. DS785UM1 EP93xx User’s Guide Figure 10-4. Edge-triggered DREQ Mode...

5-34 DS785UM1Copyright 2007 Cirrus LogicSystem ControllerEP93xx User’s Guide555SysCfg Address:0x8093_009C - Read/Write, Software lockedDefault:0x0000_

DS785UM1 5-35Copyright 2007 Cirrus Logic System ControllerEP93xx User’s Guide555LCSn1, LCSn2: Define Watchdog startup action:00 - Watchdog disabled, R

5-36 DS785UM1Copyright 2007 Cirrus LogicSystem ControllerEP93xx User’s Guide555

DS785UM1 6-1Copyright 2007 Cirrus Logic 666Chapter 66Vectored Interrupt Controller 6.1 IntroductionThe EP93xx processors contain two cascaded Vectore

6-2 DS785UM1Copyright 2007 Cirrus LogicVectored Interrupt ControllerEP93xx User’s Guide666 Figure 6-1. Vectored Interrupt Controller Block Diagram 6.1

DS785UM1 6-3Copyright 2007 Cirrus Logic Vectored Interrupt ControllerEP93xx User’s Guide666Any 16 of the 32 interrupts (per VIC) can be designated as

6-4 DS785UM1Copyright 2007 Cirrus LogicVectored Interrupt ControllerEP93xx User’s Guide666 6.1.3 Interrupt DetailsDetails of the interrupts described

DS785UM1 6-5Copyright 2007 Cirrus Logic Vectored Interrupt ControllerEP93xx User’s Guide666TC1UI Timer Counter 1 Under Flow Interrupt. When Timer Coun

6-6 DS785UM1Copyright 2007 Cirrus LogicVectored Interrupt ControllerEP93xx User’s Guide666UART1TXINTR1 UART 1 Transmit Interrupt. See Chapter 14, &qu

DS785UM1 6-7Copyright 2007 Cirrus Logic Vectored Interrupt ControllerEP93xx User’s Guide666CLK1HZ 1 Hz clock interrupt. See Chapter 20, "Real Ti

DS785UM1 ©Copyright 2007 Cirrus Logic, Inc. xviiEP93xx User’s Guide Figure 25-1. Different Types of Touch Screens ...

6-8 DS785UM1Copyright 2007 Cirrus LogicVectored Interrupt ControllerEP93xx User’s Guide666INT_DSP ARM Core interrupt. GPIOINTR Combined Interrupt fr

DS785UM1 6-9Copyright 2007 Cirrus Logic Vectored Interrupt ControllerEP93xx User’s Guide666Note: The Reset Values of the VICxPeriphID[3:0] registers

6-10 DS785UM1Copyright 2007 Cirrus LogicVectored Interrupt ControllerEP93xx User’s Guide666Definition:IRQ Status Register. The VICxIRQStatus register

DS785UM1 6-11Copyright 2007 Cirrus Logic Vectored Interrupt ControllerEP93xx User’s Guide666Definition:The VICxRawIntr register provides the status of

6-12 DS785UM1Copyright 2007 Cirrus LogicVectored Interrupt ControllerEP93xx User’s Guide666Definition:Interrupt Enable Register. The VICxIntEnable reg

DS785UM1 6-13Copyright 2007 Cirrus Logic Vectored Interrupt ControllerEP93xx User’s Guide666Default: Don’t CareDefinition:Software Interrupt Register.

6-14 DS785UM1Copyright 2007 Cirrus LogicVectored Interrupt ControllerEP93xx User’s Guide666Definition:Protection Enable Register. The VICxProtection r

DS785UM1 6-15Copyright 2007 Cirrus Logic Vectored Interrupt ControllerEP93xx User’s Guide666If you are not using the priority level in the VIC, write

6-16 DS785UM1Copyright 2007 Cirrus LogicVectored Interrupt ControllerEP93xx User’s Guide666VICxVectAddr7,VICxVectAddr8,VICxVectAdd9,VICxVectAddr10,VIC

DS785UM1 6-17Copyright 2007 Cirrus Logic Vectored Interrupt ControllerEP93xx User’s Guide666VIC2VectAddr6: 0x800C_0118 - Read/WriteVIC2VectAddr7: 0x80

xviii ©Copyright 2007 Cirrus Logic, Inc. DS785UM1 EP93xx User’s GuideTable 3-6. LDC/STC Opcode Map ...

6-18 DS785UM1Copyright 2007 Cirrus LogicVectored Interrupt ControllerEP93xx User’s Guide666VICxVectCntl15 Address:VIC1VectCntl0: 0x800B_0200 - Read

DS785UM1 6-19Copyright 2007 Cirrus Logic Vectored Interrupt ControllerEP93xx User’s Guide666Note: Vectored interrupts are only generated if the inter

6-20 DS785UM1Copyright 2007 Cirrus LogicVectored Interrupt ControllerEP93xx User’s Guide666

DS785UM1 7-1Copyright 2007 Cirrus Logic Raster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777Chapter 77Raster Engine Wit

7-2 DS785UM1Copyright 2007 Cirrus LogicRaster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777The Raster engine also suppo

DS785UM1 7-3Copyright 2007 Cirrus Logic Raster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777Since the frame buffer is s

7-4 DS785UM1Copyright 2007 Cirrus LogicRaster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777to one pixel combination bli

DS785UM1 7-5Copyright 2007 Cirrus Logic Raster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777most significant location o

7-6 DS785UM1Copyright 2007 Cirrus LogicRaster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777 7.3.5 Frame Buffer Memory

DS785UM1 7-7Copyright 2007 Cirrus Logic Raster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777brightness control. The Bri

DS785UM1 ©Copyright 2007 Cirrus Logic, Inc. xixEP93xx User’s GuideTable 8-2. bpp Memory Organization...

7-8 DS785UM1Copyright 2007 Cirrus LogicRaster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777 Figure 7-1. Raster Engine B

DS785UM1 7-9Copyright 2007 Cirrus Logic Raster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777register, “VidScrnPage” on

7-10 DS785UM1Copyright 2007 Cirrus LogicRaster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777words on both the upper and

DS785UM1 7-11Copyright 2007 Cirrus Logic Raster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777this mode will cause an ob

7-12 DS785UM1Copyright 2007 Cirrus LogicRaster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777data into the unused LSBs o

DS785UM1 7-13Copyright 2007 Cirrus Logic Raster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777Table 7-3. Output Pixel T

DS785UM1 7-14Copyright 2007 Cirrus Logic Raster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777*These bits are an ORed c

DS785UM1 7-15Copyright 2007 Cirrus Logic Raster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777 7.4.8 Grayscale/Color Ge

7-16 DS785UM1Copyright 2007 Cirrus LogicRaster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777Assuming that pixel input v

DS785UM1 7-17Copyright 2007 Cirrus Logic Raster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777 7.4.8.7 Grayscale Look-Up

DS785UM1 ©Copyright 2007 Cirrus Logic, Inc. iiEP93xx User’s GuideContacting Cirrus Logic SupportFor all product questions and inquiries contact a Cirr

xx ©Copyright 2007 Cirrus Logic, Inc. DS785UM1 EP93xx User’s GuideTable 11-1. Frame Bandwidth Allocation ...

7-18 DS785UM1Copyright 2007 Cirrus LogicRaster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777Where FRAME[1:0] = FRAME_CN

DS785UM1 7-19Copyright 2007 Cirrus Logic Raster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777At clock 0, the HCNT, VCNT

7-20 DS785UM1Copyright 2007 Cirrus LogicRaster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777The values in between full

DS785UM1 7-21Copyright 2007 Cirrus Logic Raster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777 Figure 7-4. Sample Matrix

7-22 DS785UM1Copyright 2007 Cirrus LogicRaster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777Assuming the 3 bit input pa

DS785UM1 7-23Copyright 2007 Cirrus Logic Raster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777Please note that as the fr

7-24 DS785UM1Copyright 2007 Cirrus LogicRaster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777 Figure 7-8. Three and Four

DS785UM1 7-25Copyright 2007 Cirrus Logic Raster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777“Start” is the beginning w

7-26 DS785UM1Copyright 2007 Cirrus LogicRaster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777The X location value contro

DS785UM1 7-27Copyright 2007 Cirrus Logic Raster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777CLINSSix bits select the h

DS785UM1 ©Copyright 2007 Cirrus Logic, Inc. xxiEP93xx User’s GuideTable 17-5. UART2 / IrDA Modes ...

7-28 DS785UM1Copyright 2007 Cirrus LogicRaster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777 7.4.10 Video TimingThe vid

DS785UM1 7-29Copyright 2007 Cirrus Logic Raster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777 Figure 7-9. Progressive/D

7-30 DS785UM1Copyright 2007 Cirrus LogicRaster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777 Figure 7-10. Interlaced Vi

DS785UM1 7-31Copyright 2007 Cirrus Logic Raster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777 7.4.10.1 Setting the Vide

7-32 DS785UM1Copyright 2007 Cirrus LogicRaster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777VLineStep = 640 x 4bpp/32 7

DS785UM1 7-33Copyright 2007 Cirrus Logic Raster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777 7.4.11.2.1 PattrnMask Re

7-34 DS785UM1Copyright 2007 Cirrus LogicRaster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777If the LUT is enabled, the

DS785UM1 7-35Copyright 2007 Cirrus Logic Raster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide7771. The MSB is dropped2.The

7-36 DS785UM1Copyright 2007 Cirrus LogicRaster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777 7.5 RegistersTable 7-12.

DS785UM1 7-37Copyright 2007 Cirrus Logic Raster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777Note: The raster engine re

xxii ©Copyright 2007 Cirrus Logic, Inc. DS785UM1 EP93xx User’s GuideTable 28-5. GPIO Register Address Map...

7-38 DS785UM1Copyright 2007 Cirrus LogicRaster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777Vertical Frame Timing Regis

DS785UM1 7-39Copyright 2007 Cirrus Logic Raster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777When the Vertical counter

7-40 DS785UM1Copyright 2007 Cirrus LogicRaster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777VBlankStrtStop Address: 0x8

DS785UM1 7-41Copyright 2007 Cirrus Logic Raster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777VClkStrtStop Address: 0x80

7-42 DS785UM1Copyright 2007 Cirrus LogicRaster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777Horizontal Frame Timing Reg

DS785UM1 7-43Copyright 2007 Cirrus Logic Raster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777The STOP value is the hori

7-44 DS785UM1Copyright 2007 Cirrus LogicRaster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777STRT: Start - Read/WriteThe

DS785UM1 7-45Copyright 2007 Cirrus Logic Raster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777HClkStrtStop Address: 0x80

7-46 DS785UM1Copyright 2007 Cirrus LogicRaster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777Frame Buffer Memory Configu

DS785UM1 7-47Copyright 2007 Cirrus Logic Raster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777PAGE: Video Screen Half-p

DS785UM1 P-1Copyright 2007 Cirrus Logic PPPChapter P17Preface P.1 About the EP93xx User’s GuideThis EP93xx User’s Guide describes the architecture, h

7-48 DS785UM1Copyright 2007 Cirrus LogicRaster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777LEN: Length - Read/WriteThe

DS785UM1 7-49Copyright 2007 Cirrus Logic Raster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777LineCarry Address: 0x8003_

7-50 DS785UM1Copyright 2007 Cirrus LogicRaster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777If the Offset value is 0x0,

DS785UM1 7-51Copyright 2007 Cirrus Logic Raster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777VideoAttribs Address: 0x80

7-52 DS785UM1Copyright 2007 Cirrus LogicRaster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777DHORZ: Double Horizontal -

DS785UM1 7-53Copyright 2007 Cirrus Logic Raster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777V_CSYNC --> D7 (Smart P

7-54 DS785UM1Copyright 2007 Cirrus LogicRaster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide7771 - Pixel data output chang

DS785UM1 7-55Copyright 2007 Cirrus Logic Raster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777PCLKEN: Pixel Clock Enable

7-56 DS785UM1Copyright 2007 Cirrus LogicRaster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777ACRateAddress: 0x8003_0214D

DS785UM1 7-57Copyright 2007 Cirrus Logic Raster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777This field should be writt

P-2 DS785UM1Copyright 2007 Cirrus Logic PrefaceEP93xx User’s GuidePPP6: Vectored Interrupt Controller X X X X X7: Raster Engine with Analog and LCD In

7-58 DS785UM1Copyright 2007 Cirrus LogicRaster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777Writing a Dual Scan value t

DS785UM1 7-59Copyright 2007 Cirrus Logic Raster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777S: Shift - Read/WriteThe

7-60 DS785UM1Copyright 2007 Cirrus LogicRaster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777ParllIfOutAddress: 0x8003_0

DS785UM1 7-61Copyright 2007 Cirrus Logic Raster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777P3 --> D3P[2:0] -->

7-62 DS785UM1Copyright 2007 Cirrus LogicRaster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777Smart Panel R/W and RS sign

DS785UM1 7-63Copyright 2007 Cirrus Logic Raster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777Blink Control RegistersBli

7-64 DS785UM1Copyright 2007 Cirrus LogicRaster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777Bit Descriptions:RSVD: Res

DS785UM1 7-65Copyright 2007 Cirrus Logic Raster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777PattrnMask Address: 0x8003

7-66 DS785UM1Copyright 2007 Cirrus LogicRaster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777Bit Descriptions:RSVD: Res

DS785UM1 7-67Copyright 2007 Cirrus Logic Raster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777CursorAdrReset Address: 0x

DS785UM1 P-3Copyright 2007 Cirrus LogicPrefaceEP93xx User’s GuidePPPNote:“X” means Function is included; “-” means Function is not included P.2 Relat

7-68 DS785UM1Copyright 2007 Cirrus LogicRaster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777CursorSizeAddress: 0x8003_0

DS785UM1 7-69Copyright 2007 Cirrus Logic Raster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide77700 - Display 1 word (16 pi

7-70 DS785UM1Copyright 2007 Cirrus LogicRaster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777CursorXYLoc Address: 0x8003

DS785UM1 7-71Copyright 2007 Cirrus Logic Raster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777The X Location value writt

7-72 DS785UM1Copyright 2007 Cirrus LogicRaster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777When Dual Scan mode is enab

DS785UM1 7-73Copyright 2007 Cirrus Logic Raster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777When EN = ‘0’ and the 2-bi

7-74 DS785UM1Copyright 2007 Cirrus LogicRaster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777Writing a Frame Counter Sel

DS785UM1 7-75Copyright 2007 Cirrus Logic Raster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777Writing ‘1’s to these Matr

7-76 DS785UM1Copyright 2007 Cirrus LogicRaster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777Where: FRAME[1:0] = FRAME_C

DS785UM1 7-77Copyright 2007 Cirrus Logic Raster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777ColorLUTAddress: 0x8003_04

P-4 DS785UM1Copyright 2007 Cirrus Logic PrefaceEP93xx User’s GuidePPP• Registers are named using mixed upper and lower case alphanumeric, for example,

7-78 DS785UM1Copyright 2007 Cirrus LogicRaster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777Bit Descriptions:RSVD: Res

DS785UM1 7-79Copyright 2007 Cirrus Logic Raster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777CLKEN: Clock Enable - Rea

7-80 DS785UM1Copyright 2007 Cirrus LogicRaster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777Bit Descriptions:RSVD: Res

DS785UM1 7-81Copyright 2007 Cirrus Logic Raster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777The STRT value is the valu

7-82 DS785UM1Copyright 2007 Cirrus LogicRaster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777

DS785UM1 8-1Copyright 2007 Cirrus Logic 888Chapter 88Graphics Accelerator 8.1 OverviewNote: The chapter applies only to the EP9307 and EP9315 proceso

8-2 DS785UM1 Copyright 2007 Cirrus LogicGraphics AcceleratorEP93xx User’s Guide888 8.2.1 CopyIt is possible to copy data from the source memory to th

DS785UM1 8-3Copyright 2007 Cirrus Logic Graphics AcceleratorEP93xx User’s Guide8882. Logical Destination 3. Transparency 8.2.2 Remapping The Graphic

8-4 DS785UM1 Copyright 2007 Cirrus LogicGraphics AcceleratorEP93xx User’s Guide888 8.3.1 Breshenham Line Draws Based on Breshenham's algorithm,

DS785UM1 8-5Copyright 2007 Cirrus Logic Graphics AcceleratorEP93xx User’s Guide888 8.4.1 Memory Organization for 1 Bit Per Pixel (bpp)The 1 bpp stor

DS785UM1 P-5Copyright 2007 Cirrus LogicPrefaceEP93xx User’s GuidePPPREV: Revision, reads chip Version number: 0 - Rev A, 1 - Rev B, 2 - Rev C, 3 - Rev

8-6 DS785UM1 Copyright 2007 Cirrus LogicGraphics AcceleratorEP93xx User’s Guide888 8.4.4 Memory Organization for 16-Bits Per PixelThe 16 bpp storag

DS785UM1 8-7Copyright 2007 Cirrus Logic Graphics AcceleratorEP93xx User’s Guide888 8.4.5 Memory Organization for 24-Bits Per PixelThe 24 bpp packed o

8-8 DS785UM1 Copyright 2007 Cirrus LogicGraphics AcceleratorEP93xx User’s Guide888 8.4.6 Memory Map AccessThe Graphics Accelerator has access to the

DS785UM1 8-9Copyright 2007 Cirrus Logic Graphics AcceleratorEP93xx User’s Guide888If a Block Copy starts at pixel 3 and 10 pixels are to be copied, th

8-10 DS785UM1 Copyright 2007 Cirrus LogicGraphics AcceleratorEP93xx User’s Guide888memory and the other register, “DESTPIXELSTRT”, is used for the des

DS785UM1 8-11Copyright 2007 Cirrus Logic Graphics AcceleratorEP93xx User’s Guide888 8.5.2.2 8 BPP Word Layout For a Block Copy where 4 pixels are tran

8-12 DS785UM1 Copyright 2007 Cirrus LogicGraphics AcceleratorEP93xx User’s Guide888Let the starting SDRAM address of the destination image be 0x0044.

DS785UM1 8-13Copyright 2007 Cirrus Logic Graphics AcceleratorEP93xx User’s Guide888Note:The word count for this example would be: 6 - 1 = 5 words, sin

8-14 DS785UM1 Copyright 2007 Cirrus LogicGraphics AcceleratorEP93xx User’s Guide8883. Setup DESTLINELENGTH Register A. Determine how many pixels occup

DS785UM1 8-15Copyright 2007 Cirrus Logic Graphics AcceleratorEP93xx User’s Guide8889. Setup BLKDESTWIDTH RegisterWrite ‘abs(X2 -X1) modulo 4096, minus

P-6 DS785UM1Copyright 2007 Cirrus Logic PrefaceEP93xx User’s GuidePPP

8-16 DS785UM1 Copyright 2007 Cirrus LogicGraphics AcceleratorEP93xx User’s Guide888SPEL = [X2% 2 (pixel depth / 8-bit byte)] x 8 = [101% 2 (16-bits /

DS785UM1 8-17Copyright 2007 Cirrus Logic Graphics AcceleratorEP93xx User’s Guide888SPEL is the starting pixel position within the word that the pixel-

8-18 DS785UM1 Copyright 2007 Cirrus LogicGraphics AcceleratorEP93xx User’s Guide8887. Setup BLOCKCTRL RegisterFor (example) 16-bit pixels and Mask AND

DS785UM1 8-19Copyright 2007 Cirrus Logic Graphics AcceleratorEP93xx User’s Guide888comprise the first scan line of the source image.For example, Table

8-20 DS785UM1 Copyright 2007 Cirrus LogicGraphics AcceleratorEP93xx User’s Guide888refer to the note in Section 8.5.2.4 on page 8-12.E. Write the desi

DS785UM1 8-21Copyright 2007 Cirrus Logic Graphics AcceleratorEP93xx User’s Guide888 8.6.4.1 Example of Block CopyTo achieve the following display and

8-22 DS785UM1 Copyright 2007 Cirrus LogicGraphics AcceleratorEP93xx User’s Guide888 8.7 Registers Note: Graphics Accelerator registers are intended t

DS785UM1 8-23Copyright 2007 Cirrus Logic Graphics AcceleratorEP93xx User’s Guide888Register DescriptionsSRCPIXELSTRTAddress: 0x8004_0000 - Read/WriteD

8-24 DS785UM1 Copyright 2007 Cirrus LogicGraphics AcceleratorEP93xx User’s Guide888Default: 0x0000_0000Mask: 0x001F_001FDefinition: Destination Pixel

DS785UM1 8-25Copyright 2007 Cirrus Logic Graphics AcceleratorEP93xx User’s Guide888Default: 0x0000_0000Mask: 0xFFFF_FFFCDefinition: Block Source Word

DS785UM1 1-1Copyright 2007 Cirrus Logic 111Chapter 11Introduction 1.1 IntroductionThe EP93xx processors are highly integrated systems-on-a-chip that

8-26 DS785UM1 Copyright 2007 Cirrus LogicGraphics AcceleratorEP93xx User’s Guide888BLKSRCWIDTH Address: 0x8004_0010 - Read/WriteDefault: 0x0000_0000Ma

DS785UM1 8-27Copyright 2007 Cirrus Logic Graphics AcceleratorEP93xx User’s Guide888The value in this field specifies the number of 32 bit words, minus

8-28 DS785UM1 Copyright 2007 Cirrus LogicGraphics AcceleratorEP93xx User’s Guide888For Line Draw functions, the method to determine the value of WIDTH

DS785UM1 8-29Copyright 2007 Cirrus Logic Graphics AcceleratorEP93xx User’s Guide888DESTLINELENGTH Address: 0x8004_0020 - Read/WriteDefault: 0x0000_000

8-30 DS785UM1 Copyright 2007 Cirrus LogicGraphics AcceleratorEP93xx User’s Guide888BLOCKCTRL Address: 0x8004_0024 - Read/WriteDefault: 0x0000_0000Mask

DS785UM1 8-31Copyright 2007 Cirrus Logic Graphics AcceleratorEP93xx User’s Guide888ERROR: Error Indicator - Read/Write1 - Bus error has occurred0 - No

8-32 DS785UM1 Copyright 2007 Cirrus LogicGraphics AcceleratorEP93xx User’s Guide888‘1’ - Pixel Expansion Mapping Function enabled‘0’ - Pixel Expansion

DS785UM1 8-33Copyright 2007 Cirrus Logic Graphics AcceleratorEP93xx User’s Guide888DYDIR = ‘0’ - Down in YFor a Line Draw function:DXDIR = ‘1’ - If X2

8-34 DS785UM1 Copyright 2007 Cirrus LogicGraphics AcceleratorEP93xx User’s Guide888TRANSPATTRN Address: 0x8004_0028 - Read/WriteDefault: 0x0000_0000Ma

DS785UM1 8-35Copyright 2007 Cirrus Logic Graphics AcceleratorEP93xx User’s Guide888MASK: Mask - Read/WriteFor a Block Copy function, the value in thi

DS785UM1 ©Copyright 2007 Cirrus Logic, Inc. iiiEP93xx User’s GuideContentsChapter Figures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-2 DS785UM1Copyright 2007 Cirrus LogicIntroductionEP93xx User’s Guide111Note:“X” means that the function is included; “-” means that the function is

8-36 DS785UM1 Copyright 2007 Cirrus LogicGraphics AcceleratorEP93xx User’s Guide888LINEINC Address: 0x8004_00343 - Read/WriteDefault: 0x0000_0000Mask:

DS785UM1 8-37Copyright 2007 Cirrus Logic Graphics AcceleratorEP93xx User’s Guide888Bit Descriptions:RSVD: Reserved - Unknown during readYINIT: Y Ini

8-38 DS785UM1 Copyright 2007 Cirrus LogicGraphics AcceleratorEP93xx User’s Guide888If BG = ‘1’ in the BLOCKCTRL register, a ‘0’ causes a pixel fill fr

DS785UM1 9-1Copyright 2007 Cirrus Logic 999Chapter 991/10/100 Mbps Ethernet LAN Controller 9.1 IntroductionThe Ethernet LAN Controller incorporates a

9-2 DS785UM1Copyright 2007 Cirrus Logic1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999The Descriptor Processor implements the Hardware Ada

DS785UM1 9-3Copyright 2007 Cirrus Logic 1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999The RAM blocks are interleaved in the AHB address s

9-4 DS785UM1Copyright 2007 Cirrus Logic1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999 Figure 9-2. Ethernet Frame / Packet Format (Type II

DS785UM1 9-5Copyright 2007 Cirrus Logic 1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999 9.1.3 Packet Transmission ProcessThis section exp

9-6 DS785UM1Copyright 2007 Cirrus Logic1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999Complete state. Thus, the Carrier Deference state ma

DS785UM1 9-7Copyright 2007 Cirrus Logic 1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999 9.1.4 Transmit Back-OffRefer to Figure 9-3. Once

DS785UM1 1-3Copyright 2007 Cirrus Logic IntroductionEP93xx User’s Guide111 Figure 1-2. EP9302 Block Diagram Figure 1-3. EP9307 Block Diagram5-Channel

9-8 DS785UM1Copyright 2007 Cirrus Logic1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999The resultant 32 bit field is transmitted on the lin

DS785UM1 9-9Copyright 2007 Cirrus Logic 1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999 9.1.4.6 Hash FilterThe 64 bit Logical Address Filt

9-10 DS785UM1Copyright 2007 Cirrus Logic1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999The relationship of RXCtl.MA and RXCtl.IAHA is show

DS785UM1 9-11Copyright 2007 Cirrus Logic 1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999To comply with the standard, pause frames should o

9-12 DS785UM1Copyright 2007 Cirrus Logic1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999most PHYs require a preamble for access to the PHY&

DS785UM1 9-13Copyright 2007 Cirrus Logic 1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999 9.1.4.11.4 Steps for PHY Startup1. Set the MDC C

9-14 DS785UM1Copyright 2007 Cirrus Logic1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999of buffers as they are exchanged with the MAC. When

DS785UM1 9-15Copyright 2007 Cirrus Logic 1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999Receive Descriptor Format - First Word Definition:

9-16 DS785UM1Copyright 2007 Cirrus Logic1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999 9.2.3 Receive Status QueueThe receive status queu

DS785UM1 9-17Copyright 2007 Cirrus Logic 1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999 Figure 9-8. Receive Status Queue Receive status

1-4 DS785UM1Copyright 2007 Cirrus LogicIntroductionEP93xx User’s Guide111 Figure 1-4. EP9312 Block Diagram Figure 1-5. EP9315 Block Diagram8-Wire Touc

9-18 DS785UM1Copyright 2007 Cirrus Logic1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999If both EOF and EOB bits are zero, the entry was ma

DS785UM1 9-19Copyright 2007 Cirrus Logic 1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999EOF: End Of Frame. When this bit is set, the assoc

9-20 DS785UM1Copyright 2007 Cirrus Logic1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999HTI: Hash Table Index. If the frame was accepted as

DS785UM1 9-21Copyright 2007 Cirrus Logic 1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999 9.2.3.2 Receive Flow Figure 9-9. Receive Flow Dia

9-22 DS785UM1Copyright 2007 Cirrus Logic1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999Refer to the circled numbers in Figure 9-9. The det

DS785UM1 9-23Copyright 2007 Cirrus Logic 1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999 9.2.3.4 Receive Descriptor Data/Status Flow Figur

9-24 DS785UM1Copyright 2007 Cirrus Logic1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999 9.2.3.5 Receive Descriptor Example Figure 9-11. Re

DS785UM1 9-25Copyright 2007 Cirrus Logic 1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999 9.2.3.6 Receive Frame Pre-ProcessingThe MAC pre-p

9-26 DS785UM1Copyright 2007 Cirrus Logic1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999 9.2.3.7 Transmit Descriptor Processor QueuesThe tr

DS785UM1 9-27Copyright 2007 Cirrus Logic 1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999 Figure 9-13. Transmit Descriptor Format and Data

DS785UM1 1-5Copyright 2007 Cirrus Logic IntroductionEP93xx User’s Guide111Features of the EP93xx processors are: • ARM920T Core: • 200 MHz maximum run

9-28 DS785UM1Copyright 2007 Cirrus Logic1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999 Figure 9-14. Multiple Fragments Per Transmit Frame

DS785UM1 9-29Copyright 2007 Cirrus Logic 1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999Bit Descriptions:TBA: Transmit Buffer Address. The

9-30 DS785UM1Copyright 2007 Cirrus Logic1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999TBL: Transmit Buffer Length. This field contains th

DS785UM1 9-31Copyright 2007 Cirrus Logic 1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999 Figure 9-15. Transmit Status Queue Transmit St

9-32 DS785UM1Copyright 2007 Cirrus Logic1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999 9.2.3.11 Transmit Status FormatOnly one Transmit S

DS785UM1 9-33Copyright 2007 Cirrus Logic 1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999NColl: Number of Collisions. This field contains t

9-34 DS785UM1Copyright 2007 Cirrus Logic1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999 9.2.3.12 Transmit Flow Figure 9-16. Transmit Flow

DS785UM1 9-35Copyright 2007 Cirrus Logic 1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999Refer to Figure 9-16. The detailed transmit flow i

9-36 DS785UM1Copyright 2007 Cirrus Logic1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999 9.2.3.14 Transmit Descriptor Data/Status Flow Figu

DS785UM1 9-37Copyright 2007 Cirrus Logic 1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999 9.2.4 Interrupts 9.2.4.1 Interrupt ProcessingInt

1-6 DS785UM1Copyright 2007 Cirrus LogicIntroductionEP93xx User’s Guide111- Block Copy- Block Fill• Touch Screen interface- 5-ADC in EP9301 and 9302 on

9-38 DS785UM1Copyright 2007 Cirrus Logic1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide99914.Wait for RxAct (BMSts) to be set, and then enque

DS785UM1 9-39Copyright 2007 Cirrus Logic 1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide9991. RxMiss - This bit indicates that the receive fr

9-40 DS785UM1Copyright 2007 Cirrus Logic1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide99910.Wait for TxAct in BMSts to be set and then write

DS785UM1 9-41Copyright 2007 Cirrus Logic 1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999Control Register DescriptionRXCtl Address:0x8001_0

9-42 DS785UM1Copyright 2007 Cirrus Logic1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999Chip Reset:0x0000_0x0xRx Reset:0x0000_0000Soft Rese

DS785UM1 9-43Copyright 2007 Cirrus Logic 1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999RxFCE1: Rx Flow Control Enable, bit 1. Setting the

9-44 DS785UM1Copyright 2007 Cirrus Logic1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999IAHA: Individual Address Hash Accept. When set, rec

DS785UM1 9-45Copyright 2007 Cirrus Logic 1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999Soft Reset:0x0000_0000Definition:Transmit Control

9-46 DS785UM1Copyright 2007 Cirrus Logic1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999PB: Pause Busy: This bit remains set as long as a p

DS785UM1 9-47Copyright 2007 Cirrus Logic 1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999The following procedure will correctly set the Sel

DS785UM1 1-7Copyright 2007 Cirrus Logic IntroductionEP93xx User’s Guide111• 16 in EP9312 only• 24 in EP9315 only 1.3 EP93xx Processor Applications Th

9-48 DS785UM1Copyright 2007 Cirrus Logic1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999RESET: Soft Reset. This is an act-once bit. When se

DS785UM1 9-49Copyright 2007 Cirrus Logic 1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999DiagDa Address:0x8001_003C - Read/WriteChip Reset:

9-50 DS785UM1Copyright 2007 Cirrus Logic1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999Bit Descriptions:GTC: General Timer Count, read onl

DS785UM1 9-51Copyright 2007 Cirrus Logic 1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999FCF Address:0x8001_0048 - Read/WriteChip Reset:0x0

9-52 DS785UM1Copyright 2007 Cirrus Logic1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide9995. Pause time = Transmit Pause Time (FCF) (2bytes)6

DS785UM1 9-53Copyright 2007 Cirrus Logic 1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999IndAd Address:0x8001_0050 through 0x8001_0055 - 6

9-54 DS785UM1Copyright 2007 Cirrus Logic1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999HashTbl Address:0x8001_0050 through 0x8001_0057 - 8

DS785UM1 9-55Copyright 2007 Cirrus Logic 1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999TXCollCnt Address:0x8001_0070 - Read OnlyChip Rese

9-56 DS785UM1Copyright 2007 Cirrus Logic1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999Definition:Receive Miss Count RegisterBit Descripti

DS785UM1 9-57Copyright 2007 Cirrus Logic 1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999TestCtl Address:0x8001_0008 - Read/WriteChip Reset

1-8 DS785UM1Copyright 2007 Cirrus LogicIntroductionEP93xx User’s Guide111processor simplifies the end-user’s programming task by using predefined co-p

9-58 DS785UM1Copyright 2007 Cirrus Logic1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999Address:0x8001_0024 - Read/WriteChip Reset:0x0000_0

DS785UM1 9-59Copyright 2007 Cirrus Logic 1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999MOIE: Receive Miss Overflow Interrupt Enable. If r

9-60 DS785UM1Copyright 2007 Cirrus Logic1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999IntStsP/IntStsC Address:0x8001_0028, for IntStsP -

DS785UM1 9-61Copyright 2007 Cirrus Logic 1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999RxMI: RxMI is set when a receive frame was discard

9-62 DS785UM1Copyright 2007 Cirrus Logic1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999RxROI: When a runt frame is received with a CRC err

DS785UM1 9-63Copyright 2007 Cirrus Logic 1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999Definition:Global Interrupt Status RegisterBit Des

9-64 DS785UM1Copyright 2007 Cirrus Logic1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999GlIntROSts Address:0x8001_0068 - Read OnlyChip Re

DS785UM1 9-65Copyright 2007 Cirrus Logic 1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999Bit Descriptions:RSVD: Reserved. Unknown During Re

9-66 DS785UM1Copyright 2007 Cirrus Logic1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999PHYAD: PHY Address. This field defines which extern

DS785UM1 9-67Copyright 2007 Cirrus Logic 1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999Soft Reset:0x0000_0000Definition:MII Status Regist

DS785UM1 1-9Copyright 2007 Cirrus Logic IntroductionEP93xx User’s Guide111 1.4.5 Integrated Ethernet MAC Reduces BOM CostsThe EP93xx processors integ

9-68 DS785UM1Copyright 2007 Cirrus Logic1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999MT: Manual Transfer. Writing a one to this bit caus

DS785UM1 9-69Copyright 2007 Cirrus Logic 1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999TxEn: Transmit Enable. Writing a one to Transmit E

9-70 DS785UM1Copyright 2007 Cirrus Logic1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999RxEn: Receive Enable. Writing a one to Receive Enab

DS785UM1 9-71Copyright 2007 Cirrus Logic 1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999RxAct: Receive Active. When this bit is set, the c

9-72 DS785UM1Copyright 2007 Cirrus Logic1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999RXDQBLen Address:0x8001_0094 - Read/WriteChip Reset

DS785UM1 9-73Copyright 2007 Cirrus Logic 1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999Definition:Receive Descriptor Queue Current Length

9-74 DS785UM1Copyright 2007 Cirrus Logic1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999RXDEnq Address:0x8001_009C - Read/WriteChip Reset:0

DS785UM1 9-75Copyright 2007 Cirrus Logic 1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999Chip Reset:0x0000_0000Soft Reset:UnchangedDefiniti

9-76 DS785UM1Copyright 2007 Cirrus Logic1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999RXStsQBLen Address:0x8001_00A4 - Read/WriteChip Res

DS785UM1 9-77Copyright 2007 Cirrus Logic 1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999Definition:Receive Status Queue Current Length. Th

1-10 DS785UM1Copyright 2007 Cirrus LogicIntroductionEP93xx User’s Guide111bits wide, the SMC supports 8-bit, 16-bit, and 32-bit devices, and the SDRAM

9-78 DS785UM1Copyright 2007 Cirrus Logic1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999RXStsEnq Address:0x8001_00AC - Read/WriteChip Reset

DS785UM1 9-79Copyright 2007 Cirrus Logic 1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999Chip Reset:0x0000_0000Soft Reset:UnchangedDefiniti

9-80 DS785UM1Copyright 2007 Cirrus Logic1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999Bit Descriptions:TDBA: Transmit Descriptor Base Add

DS785UM1 9-81Copyright 2007 Cirrus Logic 1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999Soft Reset:UnchangedDefinition:Transmit Descriptor

9-82 DS785UM1Copyright 2007 Cirrus Logic1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999TXDEnq Address:0x8001_00BC - Read/WriteChip Reset:0

DS785UM1 9-83Copyright 2007 Cirrus Logic 1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide9990x0000_0000Soft Reset:UnchangedDefinition:Transmit

9-84 DS785UM1Copyright 2007 Cirrus Logic1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999TXStsQCurLen Address:0x8001_00C6 - Read/Write. Note

DS785UM1 9-85Copyright 2007 Cirrus Logic 1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999Definition:Transmit Status Queue Current Address.

9-86 DS785UM1Copyright 2007 Cirrus Logic1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999RDST: Receive Data Soft Threshold. The hard and sof

DS785UM1 9-87Copyright 2007 Cirrus Logic 1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999TDST: Transmit Data Soft Threshold. The hard and s

DS785UM1 2-1Copyright 2007 Cirrus Logic 222Chapter 22ARM920T Core and Advanced High-Speed Bus (AHB) 2.1 IntroductionThis chapter describes the ARM920

9-88 DS785UM1Copyright 2007 Cirrus Logic1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999The hard and soft threshold work in exactly the sam

DS785UM1 9-89Copyright 2007 Cirrus Logic 1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999The hard and soft threshold work in exactly the sa

9-90 DS785UM1Copyright 2007 Cirrus Logic1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999RDST: Receive Descriptor Soft Threshold. The hard a

DS785UM1 9-91Copyright 2007 Cirrus Logic 1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999TDST: Transmit Descriptor Soft Threshold. The hard

9-92 DS785UM1Copyright 2007 Cirrus Logic1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999TST: Transmit Start Threshold. The transmit start t

DS785UM1 10-1Copyright 2007 Cirrus Logic 101010Chapter 1010DMA Controller 10.1 IntroductionThe DMA Controller can be used to interface streams from 20

10-2 DS785UM1Copyright 2007 Cirrus LogicDMA ControllerEP93xx User’s Guide101010• Five hardware requests for M2M transfers; 2 for external peripherals

DS785UM1 10-3Copyright 2007 Cirrus Logic DMA ControllerEP93xx User’s Guide101010The DMA controller memory-to-memory channels can also be used in “Memo

10-4 DS785UM1Copyright 2007 Cirrus LogicDMA ControllerEP93xx User’s Guide101010The transaction is initiated by a SSP or IDE request.This request is ma

DS785UM1 10-5Copyright 2007 Cirrus Logic DMA ControllerEP93xx User’s Guide101010occurred. If the ICE bit is not set, then the DMA flushes the last goo

iv ©Copyright 2007 Cirrus Logic, Inc. DS785UM1 EP93xx User’s Guide2.3.2 AHB-to-APB Bridge ...

2-2 DS785UM1Copyright 2007 Cirrus LogicARM920T Core and Advanced High-Speed Bus (AHB)EP93xx User’s Guide222 2.2.2 Block Diagram Figure 2-1. ARM920T B

10-6 DS785UM1Copyright 2007 Cirrus LogicDMA ControllerEP93xx User’s Guide101010 10.1.5.2 Hardware Trigger Mode for Internal Peripherals (SSP and IDE)

DS785UM1 10-7Copyright 2007 Cirrus Logic DMA ControllerEP93xx User’s Guide101010The data received on each of the five peripheral receive DMA Rx Data b

10-8 DS785UM1Copyright 2007 Cirrus LogicDMA ControllerEP93xx User’s Guide101010CE: Channel (Peripheral) ErrorICE: CONTROL[6] - Ignore Channel Error. T

DS785UM1 10-9Copyright 2007 Cirrus Logic DMA ControllerEP93xx User’s Guide101010 10.1.9.2 Data Transfer Initiation and TerminationThe DMA Controller i

10-10 DS785UM1Copyright 2007 Cirrus LogicDMA ControllerEP93xx User’s Guide101010 10.1.10 M2M DMA Functional Description 10.1.10.1 M2M DMA Control Fini

DS785UM1 10-11Copyright 2007 Cirrus Logic DMA ControllerEP93xx User’s Guide101010No data transfers occur in this state. 10.1.10.1.3 DMA_MEM_RDThe DMA

10-12 DS785UM1Copyright 2007 Cirrus LogicDMA ControllerEP93xx User’s Guide101010 10.1.10.1.5 DMA_BWC_WAITThe DMA M2M Control FSM enters the DMA_BWC_WA

DS785UM1 10-13Copyright 2007 Cirrus Logic DMA ControllerEP93xx User’s Guide101010(which BCRx is free can be determined using the STATUS.Nextbuffer sta

10-14 DS785UM1Copyright 2007 Cirrus LogicDMA ControllerEP93xx User’s Guide101010The DMA Controller initiates memory-to-memory transfers in the receive

DS785UM1 10-15Copyright 2007 Cirrus Logic DMA ControllerEP93xx User’s Guide101010• For a software-triggered M2M transfer, a memory-write is initiated

DS785UM1 2-3Copyright 2007 Cirrus Logic ARM920T Core and Advanced High-Speed Bus (AHB)EP93xx User’s Guide222A 16 kbyte instruction and a 16 kbyte data

10-16 DS785UM1Copyright 2007 Cirrus LogicDMA ControllerEP93xx User’s Guide101010When the DONE interrupt is set, the processor can then write a one to

DS785UM1 10-17Copyright 2007 Cirrus Logic DMA ControllerEP93xx User’s Guide101010Subsequent changes on DREQ are ignored until the pending request begi

10-18 DS785UM1Copyright 2007 Cirrus LogicDMA ControllerEP93xx User’s Guide101010At the start of a receive or transmit data transfer, the AHB Master In

DS785UM1 10-19Copyright 2007 Cirrus Logic DMA ControllerEP93xx User’s Guide101010 10.1.12.1 Internal M2P/P2M Channel Rx Buffer DescriptorsOnly one Rx

10-20 DS785UM1Copyright 2007 Cirrus LogicDMA ControllerEP93xx User’s Guide101010During normal operation, using the “fair” rotating priority scheme sho

DS785UM1 10-21Copyright 2007 Cirrus Logic DMA ControllerEP93xx User’s Guide101010 10.2.2 Internal M2P/P2M Channel Register MapThe DMA Memory Map above

10-22 DS785UM1Copyright 2007 Cirrus LogicDMA ControllerEP93xx User’s Guide101010Register DescriptionsCONTROLAddress:Channel Base Address + 0x0000 - Re

DS785UM1 10-23Copyright 2007 Cirrus Logic DMA ControllerEP93xx User’s Guide101010ABORT: This bit determines how the DMA Channel State machine behaves

10-24 DS785UM1Copyright 2007 Cirrus LogicDMA ControllerEP93xx User’s Guide101010NOTE: The naming convention used for channels and ports is as follows

DS785UM1 10-25Copyright 2007 Cirrus Logic DMA ControllerEP93xx User’s Guide101010INTERRUPT Address:Channel Base Address + 0x0004 - Read/WriteDefinitio

2-4 DS785UM1Copyright 2007 Cirrus LogicARM920T Core and Advanced High-Speed Bus (AHB)EP93xx User’s Guide222 2.2.3.2 Memory Management UnitThe MMU prov

10-26 DS785UM1Copyright 2007 Cirrus LogicDMA ControllerEP93xx User’s Guide101010STATUS Address:Channel Base Address + 0x000C - Read OnlyDefinition:Thi

DS785UM1 10-27Copyright 2007 Cirrus Logic DMA ControllerEP93xx User’s Guide101010Current State: Indicates the state that the Channel FSM is currently

10-28 DS785UM1Copyright 2007 Cirrus LogicDMA ControllerEP93xx User’s Guide101010REMAINAddress:Channel Base Address + 0x0014 - Read OnlyDefinition:The

DS785UM1 10-29Copyright 2007 Cirrus Logic DMA ControllerEP93xx User’s Guide101010MAXCNTx Address:MAXCNT0: Channel Base Address + 0x0020 - Read/WriteMA

10-30 DS785UM1Copyright 2007 Cirrus LogicDMA ControllerEP93xx User’s Guide101010CURRENTx Address:CURRENT0: Channel Base Address + 0x0028 - Read Only

DS785UM1 10-31Copyright 2007 Cirrus Logic DMA ControllerEP93xx User’s Guide101010Note:See Table 10-3 for Channel Base AddressesNote:* Write this locat

10-32 DS785UM1Copyright 2007 Cirrus LogicDMA ControllerEP93xx User’s Guide101010of the source and destination addresses to avoid any problems in the c

DS785UM1 10-33Copyright 2007 Cirrus Logic DMA ControllerEP93xx User’s Guide101010Example: if BWC = 1010b (indicating 1024 bytes, see Table 10-9, below

10-34 DS785UM1Copyright 2007 Cirrus LogicDMA ControllerEP93xx User’s Guide101010DAH: Destination Address Hold - This bit is used for external M2P tran

DS785UM1 10-35Copyright 2007 Cirrus Logic DMA ControllerEP93xx User’s Guide101010NFBIntEn: Setting this bit to “1” enables the generation of the NFB

DS785UM1 2-5Copyright 2007 Cirrus Logic ARM920T Core and Advanced High-Speed Bus (AHB)EP93xx User’s Guide222 2.2.3.2.3 MMU EnableEnabling the MMU all

10-36 DS785UM1Copyright 2007 Cirrus LogicDMA ControllerEP93xx User’s Guide101010Definition:This is the interrupt status register. The register is read

DS785UM1 10-37Copyright 2007 Cirrus Logic DMA ControllerEP93xx User’s Guide101010STATUS Address:Channel Base Address + 0x000C - Read/WriteDefinition:T

10-38 DS785UM1Copyright 2007 Cirrus LogicDMA ControllerEP93xx User’s Guide101010CurrentState: Indicates the states that the M2M Channel Control FSM an

DS785UM1 10-39Copyright 2007 Cirrus Logic DMA ControllerEP93xx User’s Guide101010EOTS: End-Of-Transfer status (valid only if the DEOT/TC pin has been

10-40 DS785UM1Copyright 2007 Cirrus LogicDMA ControllerEP93xx User’s Guide101010The NextBuffer status bit can be used in conjunction with the CurrentS

DS785UM1 10-41Copyright 2007 Cirrus Logic DMA ControllerEP93xx User’s Guide101010to indicate that the external device has requested service. The STATU

10-42 DS785UM1Copyright 2007 Cirrus LogicDMA ControllerEP93xx User’s Guide101010For a double/multiple buffer transfer, the second buffer descriptor ca

DS785UM1 10-43Copyright 2007 Cirrus Logic DMA ControllerEP93xx User’s Guide101010DAR_BASEx Address:DAR_BASE0: Channel Base Address + 0x002C- Read/Writ

10-44 DS785UM1Copyright 2007 Cirrus LogicDMA ControllerEP93xx User’s Guide101010Bit Descriptions:SAR_CURRENTx: Returns the current value of the channe

DS785UM1 10-45Copyright 2007 Cirrus Logic DMA ControllerEP93xx User’s Guide101010Address:0x8000_03C0 - Read/WriteDefinition:DMA Global Interrupt Regis

2-6 DS785UM1Copyright 2007 Cirrus LogicARM920T Core and Advanced High-Speed Bus (AHB)EP93xx User’s Guide222 2.2.3.3.2 Data Cache Enable• A write to b

10-46 DS785UM1Copyright 2007 Cirrus LogicDMA ControllerEP93xx User’s Guide101010Definition:DMA Channel Arbitration Register. This bit controls the DMA

DS785UM1 11-1Copyright 2007 Cirrus Logic 111111Chapter 1111Universal Serial Bus Host Controller 11.1 IntroductionNote: The EP9301 and EP9302 processor

11-2 DS785UM1 Copyright 2007 Cirrus LogicUniversal Serial Bus Host ControllerEP93xx User’s Guide111111The Client Software/USB Device and Host Controll

DS785UM1 11-3Copyright 2007 Cirrus Logic Universal Serial Bus Host ControllerEP93xx User’s Guide111111 11.2.2 Host Controller Interface 11.2.2.1 Commu

11-4 DS785UM1 Copyright 2007 Cirrus LogicUniversal Serial Bus Host ControllerEP93xx User’s Guide111111 11.2.2.2 Data StructuresThe basic building bloc

DS785UM1 11-5Copyright 2007 Cirrus Logic Universal Serial Bus Host ControllerEP93xx User’s Guide111111scheduling the Endpoint Descriptor at the approp

11-6 DS785UM1 Copyright 2007 Cirrus LogicUniversal Serial Bus Host ControllerEP93xx User’s Guide111111 Figure 11-5. Sample Interrupt Endpoint Schedule

DS785UM1 11-7Copyright 2007 Cirrus Logic Universal Serial Bus Host ControllerEP93xx User’s Guide111111A portion of the bandwidth is reserved for nonpe

11-8 DS785UM1 Copyright 2007 Cirrus LogicUniversal Serial Bus Host ControllerEP93xx User’s Guide111111 11.2.4 Host Controller ResponsibilitiesThis sec

DS785UM1 11-9Copyright 2007 Cirrus Logic Universal Serial Bus Host ControllerEP93xx User’s Guide111111 Figure 11-6. USB Host Controller Block Diagram

DS785UM1 2-7Copyright 2007 Cirrus Logic ARM920T Core and Advanced High-Speed Bus (AHB)EP93xx User’s Guide222• Latched address and control• A simple In

11-10 DS785UM1 Copyright 2007 Cirrus LogicUniversal Serial Bus Host ControllerEP93xx User’s Guide111111 11.2.5.4 HCI Master Block The HCI Master Block

DS785UM1 11-11Copyright 2007 Cirrus Logic Universal Serial Bus Host ControllerEP93xx User’s Guide111111 11.3 RegistersThe Host Controller (HC) contain

11-12 DS785UM1 Copyright 2007 Cirrus LogicUniversal Serial Bus Host ControllerEP93xx User’s Guide111111OpenHCI Implementation Specific RegistersThe Ro

DS785UM1 11-13Copyright 2007 Cirrus Logic Universal Serial Bus Host ControllerEP93xx User’s Guide111111Definition:Controls the host controller’s opera

11-14 DS785UM1 Copyright 2007 Cirrus LogicUniversal Serial Bus Host ControllerEP93xx User’s Guide111111BLE: BulkListEnable: This bit is set to enable

DS785UM1 11-15Copyright 2007 Cirrus Logic Universal Serial Bus Host ControllerEP93xx User’s Guide111111RWE: RemoteWakeupEnable: This bit is used by HC

11-16 DS785UM1 Copyright 2007 Cirrus LogicUniversal Serial Bus Host ControllerEP93xx User’s Guide111111CLF: ControlListFilled: This bit is used to ind

DS785UM1 11-17Copyright 2007 Cirrus Logic Universal Serial Bus Host ControllerEP93xx User’s Guide111111HcInterruptStatus Address:0x8002_000CDefault:0x

11-18 DS785UM1 Copyright 2007 Cirrus LogicUniversal Serial Bus Host ControllerEP93xx User’s Guide111111FNO: FrameNumberOverflow. This bit is set when

DS785UM1 11-19Copyright 2007 Cirrus Logic Universal Serial Bus Host ControllerEP93xx User’s Guide111111FNO: FrameNumberOverflow. Enable interrupt gen

2-8 DS785UM1Copyright 2007 Cirrus LogicARM920T Core and Advanced High-Speed Bus (AHB)EP93xx User’s Guide222 Figure 2-3. Main Data PathsBefore an AMBA

11-20 DS785UM1 Copyright 2007 Cirrus LogicUniversal Serial Bus Host ControllerEP93xx User’s Guide111111FNO: FrameNumberOverflow: Disable interrupt ge

DS785UM1 11-21Copyright 2007 Cirrus Logic Universal Serial Bus Host ControllerEP93xx User’s Guide111111Default:0x0000_0000Definition:Physical address

11-22 DS785UM1 Copyright 2007 Cirrus LogicUniversal Serial Bus Host ControllerEP93xx User’s Guide111111HcControlCurrentEDAddress:0x8002_0024Default:0x

DS785UM1 11-23Copyright 2007 Cirrus Logic Universal Serial Bus Host ControllerEP93xx User’s Guide111111Physical address of the first endpoint descript

11-24 DS785UM1 Copyright 2007 Cirrus LogicUniversal Serial Bus Host ControllerEP93xx User’s Guide111111HcDoneHeadAddress:0x8002_0030Default:0x0000_000

DS785UM1 11-25Copyright 2007 Cirrus Logic Universal Serial Bus Host ControllerEP93xx User’s Guide111111RSVD: Reserved. Unknown During Read. FI: Frame

11-26 DS785UM1 Copyright 2007 Cirrus LogicUniversal Serial Bus Host ControllerEP93xx User’s Guide111111FRT: FrameRemainingToggle. This bit is loaded

DS785UM1 11-27Copyright 2007 Cirrus Logic Universal Serial Bus Host ControllerEP93xx User’s Guide1111110x8002_0040Default:0x0000_0000Definition:Define

11-28 DS785UM1 Copyright 2007 Cirrus LogicUniversal Serial Bus Host ControllerEP93xx User’s Guide111111HcRhDescriptorA Address:0x8002_0048Default:0x02

DS785UM1 11-29Copyright 2007 Cirrus Logic Universal Serial Bus Host ControllerEP93xx User’s Guide111111NPS: NoPowerSwitching. These bits are used to

DS785UM1 2-9Copyright 2007 Cirrus Logic ARM920T Core and Advanced High-Speed Bus (AHB)EP93xx User’s Guide222A write data bus is used to move data from

11-30 DS785UM1 Copyright 2007 Cirrus LogicUniversal Serial Bus Host ControllerEP93xx User’s Guide111111Default:0x0000_0000Definition:Describes the roo

DS785UM1 11-31Copyright 2007 Cirrus Logic Universal Serial Bus Host ControllerEP93xx User’s Guide111111RSVD: Reserved. Unknown During Read. LPS: (REA

11-32 DS785UM1 Copyright 2007 Cirrus LogicUniversal Serial Bus Host ControllerEP93xx User’s Guide111111HcRhPortStatusx Address:HcRhPortStatus1 - 0x800

DS785UM1 11-33Copyright 2007 Cirrus Logic Universal Serial Bus Host ControllerEP93xx User’s Guide111111PES: (READ) PortEnableStatus. This bit indicat

11-34 DS785UM1 Copyright 2007 Cirrus LogicUniversal Serial Bus Host ControllerEP93xx User’s Guide111111POCI: (READ) PortOverCurrentIndicator. This bi

DS785UM1 11-35Copyright 2007 Cirrus Logic Universal Serial Bus Host ControllerEP93xx User’s Guide111111(WRITE) SetPortPower: The HCD writes a “1” to s

11-36 DS785UM1 Copyright 2007 Cirrus LogicUniversal Serial Bus Host ControllerEP93xx User’s Guide111111OCIC: PortOverCurrentIndicatorChange. This bit

DS785UM1 11-37Copyright 2007 Cirrus Logic Universal Serial Bus Host ControllerEP93xx User’s Guide111111USBHCISts Address:0x8002_0084 - Read/WriteDef

11-38 DS785UM1 Copyright 2007 Cirrus LogicUniversal Serial Bus Host ControllerEP93xx User’s Guide111111

DS785UM1 12-1Copyright 2007 Cirrus Logic 121212Chapter 1212Static Memory Controller 12.1 IntroductionNote: In the EP9301 and 9302 processors, the comm

2-10 DS785UM1Copyright 2007 Cirrus LogicARM920T Core and Advanced High-Speed Bus (AHB)EP93xx User’s Guide222 2.2.8.1 Main AHB Bus Arbiter This Main AH

12-2 DS785UM1 Copyright 2007 Cirrus LogicStatic Memory ControllerEP93xx User’s Guide121212The SMC has five main functions: 1. Memory bank selecting 2.

DS785UM1 12-3Copyright 2007 Cirrus Logic Static Memory ControllerEP93xx User’s Guide121212 Figure 12-1. 32-bit Read, 32-bit Memory, 0 Wait Cycles, RBL

12-4 DS785UM1 Copyright 2007 Cirrus LogicStatic Memory ControllerEP93xx User’s Guide121212 Figure 12-3. 16-bit Read, 16-bit Memory, RBLE = 1, WAITn Ac

DS785UM1 12-5Copyright 2007 Cirrus Logic Static Memory ControllerEP93xx User’s Guide121212If the bit-width of an internal device that generates a read

12-6 DS785UM1 Copyright 2007 Cirrus LogicStatic Memory ControllerEP93xx User’s Guide1212121. These signals go directly to the inserted PC card.2. The

DS785UM1 12-7Copyright 2007 Cirrus Logic Static Memory ControllerEP93xx User’s Guide121212 Figure 12-5. Single PC Card InterfaceRUN nCF_MCBVD

12-8 DS785UM1 Copyright 2007 Cirrus LogicStatic Memory ControllerEP93xx User’s Guide121212 12.4 PC Card Memory-Mode Enable SignalsPC Card memory-mode

DS785UM1 12-9Copyright 2007 Cirrus Logic Static Memory ControllerEP93xx User’s Guide121212Table 12-6. Accesses to 8-Bit Attribute / Common / IO Memory

12-10 DS785UM1 Copyright 2007 Cirrus LogicStatic Memory ControllerEP93xx User’s Guide121212 12.6 Registers 12.6.1 Bank Configuration RegistersSMCBCR[7

DS785UM1 12-11Copyright 2007 Cirrus Logic Static Memory ControllerEP93xx User’s Guide121212Bit Descriptions:RSVD: Reserved - Unknown During Read IDCY:

DS785UM1 2-11Copyright 2007 Cirrus Logic ARM920T Core and Advanced High-Speed Bus (AHB)EP93xx User’s Guide222 2.2.8.2 SDRAM Slave ArbiterThe SDRAM Sla

12-12 DS785UM1 Copyright 2007 Cirrus LogicStatic Memory ControllerEP93xx User’s Guide121212The number of wait cycles for each of the 2nd, 3rd, and 4th

DS785UM1 12-13Copyright 2007 Cirrus Logic Static Memory ControllerEP93xx User’s Guide121212EBIBRKDIS: EBI Break Disable - Read/WriteThe value written

12-14 DS785UM1 Copyright 2007 Cirrus LogicStatic Memory ControllerEP93xx User’s Guide121212The data strobe assertion time is specified by (AA+1) HCLK

DS785UM1 12-15Copyright 2007 Cirrus Logic Static Memory ControllerEP93xx User’s Guide121212The value written to this field specifies the minimum ‘numb

12-16 DS785UM1 Copyright 2007 Cirrus LogicStatic Memory ControllerEP93xx User’s Guide1212120 - 8-bit wide Common space1 - 16-bit wide Common spaceAI:

DS785UM1 12-17Copyright 2007 Cirrus Logic Static Memory ControllerEP93xx User’s Guide121212PCEN: PC Card Enable - Read/WriteWriting a “1” to this bit

12-18 DS785UM1 Copyright 2007 Cirrus LogicStatic Memory ControllerEP93xx User’s Guide121212

DS785UM1 13-1Copyright 2007 Cirrus Logic 131313Chapter 1313SDRAM, SyncROM, and SyncFLASH Controller 13.1 IntroductionNote: In the EP9301 and 9302 proc

13-2 DS785UM1 Copyright 2007 Cirrus LogicSDRAM, SyncROM, and SyncFLASH ControllerEP93xx User’s Guide131313Length = 0x4 (32-bit wide memory bus) or Bur

DS785UM1 13-3Copyright 2007 Cirrus Logic SDRAM, SyncROM, and SyncFLASH ControllerEP93xx User’s Guide131313it’s data outputs in the high impedance stat

DS785UM1 ©Copyright 2007 Cirrus Logic, Inc. vEP93xx User’s Guide4.2.5 Synchronous Memory Operation...

2-12 DS785UM1Copyright 2007 Cirrus LogicARM920T Core and Advanced High-Speed Bus (AHB)EP93xx User’s Guide222 2.3.2 AHB-to-APB BridgeThe AHB-to-APB Br

13-4 DS785UM1 Copyright 2007 Cirrus LogicSDRAM, SyncROM, and SyncFLASH ControllerEP93xx User’s Guide131313the synchronous memory map. Refer to Table 1

DS785UM1 13-5Copyright 2007 Cirrus Logic SDRAM, SyncROM, and SyncFLASH ControllerEP93xx User’s Guide1313132Write a ‘1’ or ‘0’ to the External Bus Widt

13-6 DS785UM1 Copyright 2007 Cirrus LogicSDRAM, SyncROM, and SyncFLASH ControllerEP93xx User’s Guide131313 13.5 Programming Mode Register: SDRAM Or Sy

DS785UM1 13-7Copyright 2007 Cirrus Logic SDRAM, SyncROM, and SyncFLASH ControllerEP93xx User’s Guide131313Note: “RFU” means Reserved for Future Use. T

13-8 DS785UM1 Copyright 2007 Cirrus LogicSDRAM, SyncROM, and SyncFLASH ControllerEP93xx User’s Guide131313When using a 16-bit wide external memory bus

DS785UM1 13-9Copyright 2007 Cirrus Logic SDRAM, SyncROM, and SyncFLASH ControllerEP93xx User’s Guide131313to the SyncFLASH register and the associated

13-10 DS785UM1 Copyright 2007 Cirrus LogicSDRAM, SyncROM, and SyncFLASH ControllerEP93xx User’s Guide131313 13.8.2 Address/Data/Control Required by Me

DS785UM1 13-11Copyright 2007 Cirrus Logic SDRAM, SyncROM, and SyncFLASH ControllerEP93xx User’s Guide131313that AD23 is not used (needed) in either th

DS785UM1 13-12Copyright 2007 Cirrus Logic SDRAM, SyncROM, and SyncFLASH ControllerEP93xx User’s Guide131313Table 13-11. EP93xx SDRAM Address Ranges (

DS785UM1 13-13Copyright 2007 Cirrus Logic SDRAM, SyncROM, and SyncFLASH ControllerEP93xx User’s Guide13131316-Bit Wide Data Systems(Continued)0xN300_

DS785UM1 2-13Copyright 2007 Cirrus Logic ARM920T Core and Advanced High-Speed Bus (AHB)EP93xx User’s Guide222Note: Due to decoding optimization, the A

DS785UM1 13-14Copyright 2007 Cirrus Logic SDRAM, SyncROM, and SyncFLASH ControllerEP93xx User’s Guide13131332-Bit Wide Data Systems64 Mbit (32-bit wi

DS785UM1 13-15Copyright 2007 Cirrus Logic SDRAM, SyncROM, and SyncFLASH ControllerEP93xx User’s Guide131313256 Mbit (32-bit wide device) 13 x 8 x 4 b

DS785UM1 13-16Copyright 2007 Cirrus Logic SDRAM, SyncROM, and SyncFLASH ControllerEP93xx User’s Guide131313Note: , the letter "N" represent

DS785UM1 13-17Copyright 2007 Cirrus Logic SDRAM, SyncROM, and SyncFLASH ControllerEP93xx User’s Guide131313 13.9 RegistersThe Synchronous Memory contr

13-18 DS785UM1 Copyright 2007 Cirrus LogicSDRAM, SyncROM, and SyncFLASH ControllerEP93xx User’s Guide131313Register DescriptionsGlConfig Address: 0x80

DS785UM1 13-19Copyright 2007 Cirrus Logic SDRAM, SyncROM, and SyncFLASH ControllerEP93xx User’s Guide131313The CKE bit must be written to ‘0’ before t

13-20 DS785UM1 Copyright 2007 Cirrus LogicSDRAM, SyncROM, and SyncFLASH ControllerEP93xx User’s Guide131313Writing a ‘1’ to this bit, in combination w

DS785UM1 13-21Copyright 2007 Cirrus Logic SDRAM, SyncROM, and SyncFLASH ControllerEP93xx User’s Guide131313Definition:The Refresh Timer register is us

13-22 DS785UM1 Copyright 2007 Cirrus LogicSDRAM, SyncROM, and SyncFLASH ControllerEP93xx User’s Guide131313Latched nCS[7:6] pins values:Asynchronous (

DS785UM1 13-23Copyright 2007 Cirrus Logic SDRAM, SyncROM, and SyncFLASH ControllerEP93xx User’s Guide131313Definition:The four device configuration re

2-14 DS785UM1Copyright 2007 Cirrus LogicARM920T Core and Advanced High-Speed Bus (AHB)EP93xx User’s Guide222User mode in Thumb state limits access to

13-24 DS785UM1 Copyright 2007 Cirrus LogicSDRAM, SyncROM, and SyncFLASH ControllerEP93xx User’s Guide131313When writing to a SyncFLASH device, only si

DS785UM1 13-25Copyright 2007 Cirrus Logic SDRAM, SyncROM, and SyncFLASH ControllerEP93xx User’s Guide131313The value written to this bit specifies a s

13-26 DS785UM1 Copyright 2007 Cirrus LogicSDRAM, SyncROM, and SyncFLASH ControllerEP93xx User’s Guide131313 The value written to this bit specifies t

DS785UM1 14-1Copyright 2007 Cirrus Logic 141414Chapter 1414UART1 With HDLC and Modem Control Signals 14.1 IntroductionUART1 is the collection of a UAR

14-2 DS785UM1Copyright 2007 Cirrus LogicUART1 With HDLC and Modem Control SignalsEP93xx User’s Guide141414The FIFOs can be programmed to be 1 byte dee

DS785UM1 14-3Copyright 2007 Cirrus Logic UART1 With HDLC and Modem Control SignalsEP93xx User’s Guide141414 Figure 14-1. UART Block DiagramAMBAAMBAAPB

14-4 DS785UM1Copyright 2007 Cirrus LogicUART1 With HDLC and Modem Control SignalsEP93xx User’s Guide141414 14.2.1.4 Baud Rate GeneratorThe baud rate g

DS785UM1 14-5Copyright 2007 Cirrus Logic UART1 With HDLC and Modem Control SignalsEP93xx User’s Guide141414 14.2.1.10 Synchronizing Registers and Logi

14-6 DS785UM1Copyright 2007 Cirrus LogicUART1 With HDLC and Modem Control SignalsEP93xx User’s Guide141414 14.2.2.1 Error BitsThree error bits are sto

DS785UM1 14-7Copyright 2007 Cirrus Logic UART1 With HDLC and Modem Control SignalsEP93xx User’s Guide141414 14.2.3 Interrupts There are five interrupt

DS785UM1 2-15Copyright 2007 Cirrus Logic ARM920T Core and Advanced High-Speed Bus (AHB)EP93xx User’s Guide222• spsr: Saved Program Status Register con

14-8 DS785UM1Copyright 2007 Cirrus LogicUART1 With HDLC and Modem Control SignalsEP93xx User’s Guide141414• If the FIFOs are disabled (have a depth of

DS785UM1 14-9Copyright 2007 Cirrus Logic UART1 With HDLC and Modem Control SignalsEP93xx User’s Guide141414 14.4.1 Overview of HDLC ModesHDLC may oper

14-10 DS785UM1Copyright 2007 Cirrus LogicUART1 With HDLC and Modem Control SignalsEP93xx User’s Guide141414The receiver utilizes a digital PLL to sync

DS785UM1 14-11Copyright 2007 Cirrus Logic UART1 With HDLC and Modem Control SignalsEP93xx User’s Guide141414 14.4.3 HDLC TransmitIn normal operation,

14-12 DS785UM1Copyright 2007 Cirrus LogicUART1 With HDLC and Modem Control SignalsEP93xx User’s Guide141414When the last byte of data for a packet is

DS785UM1 14-13Copyright 2007 Cirrus Logic UART1 With HDLC and Modem Control SignalsEP93xx User’s Guide141414incoming address consisting entirely of “1

14-14 DS785UM1Copyright 2007 Cirrus LogicUART1 With HDLC and Modem Control SignalsEP93xx User’s Guide141414 14.4.8 DMA The DMA engine may be used with

DS785UM1 14-15Copyright 2007 Cirrus Logic UART1 With HDLC and Modem Control SignalsEP93xx User’s Guide141414The use of EGPIO[3] is determined by sever

14-16 DS785UM1Copyright 2007 Cirrus LogicUART1 With HDLC and Modem Control SignalsEP93xx User’s Guide141414 14.5.2 Bus Bandwidth RequirementsThere are

DS785UM1 14-17Copyright 2007 Cirrus Logic UART1 With HDLC and Modem Control SignalsEP93xx User’s Guide14141414.1 RegistersUART Register DescriptionsUA

2-16 DS785UM1Copyright 2007 Cirrus LogicARM920T Core and Advanced High-Speed Bus (AHB)EP93xx User’s Guide222 2.3.5 Memory Map The memory map for Sync

14-18 DS785UM1Copyright 2007 Cirrus LogicUART1 With HDLC and Modem Control SignalsEP93xx User’s Guide141414UART1RXSts Address:0x808C_0004 - Read/Write

DS785UM1 14-19Copyright 2007 Cirrus Logic UART1 With HDLC and Modem Control SignalsEP93xx User’s Guide141414FE: Framing Error. When this bit is set to

14-20 DS785UM1Copyright 2007 Cirrus LogicUART1 With HDLC and Modem Control SignalsEP93xx User’s Guide141414FEN: FIFO Enable.1 - Transmit and receive F

DS785UM1 14-21Copyright 2007 Cirrus Logic UART1 With HDLC and Modem Control SignalsEP93xx User’s Guide141414Definition:UART Line Control Register Midd

14-22 DS785UM1Copyright 2007 Cirrus LogicUART1 With HDLC and Modem Control SignalsEP93xx User’s Guide141414UART1Ctrl Address:0x808C_0014 - Read/WriteD

DS785UM1 14-23Copyright 2007 Cirrus Logic UART1 With HDLC and Modem Control SignalsEP93xx User’s Guide141414Address:0x808C_0018 - Read OnlyDefault:0x0

14-24 DS785UM1Copyright 2007 Cirrus LogicUART1 With HDLC and Modem Control SignalsEP93xx User’s Guide141414CTS: Clear To Send status. This bit is the

DS785UM1 14-25Copyright 2007 Cirrus Logic UART1 With HDLC and Modem Control SignalsEP93xx User’s Guide141414UART1DMACtrl Address:0x808C_0028 - Read/Wr

14-26 DS785UM1Copyright 2007 Cirrus LogicUART1 With HDLC and Modem Control SignalsEP93xx User’s Guide141414Default:0x0000_0000Definition:Modem Control

DS785UM1 14-27Copyright 2007 Cirrus Logic UART1 With HDLC and Modem Control SignalsEP93xx User’s Guide141414Definition:Modem Status RegisterBit Descri

DS785UM1 2-17Copyright 2007 Cirrus Logic ARM920T Core and Advanced High-Speed Bus (AHB)EP93xx User’s Guide222Note: The shaded memory areas are dedicat

14-28 DS785UM1Copyright 2007 Cirrus LogicUART1 With HDLC and Modem Control SignalsEP93xx User’s Guide141414CMAS: Clock Master: 1 - Transmitter and/or

DS785UM1 14-29Copyright 2007 Cirrus Logic UART1 With HDLC and Modem Control SignalsEP93xx User’s Guide141414RILEN: Receive Information Lost Interrupt

14-30 DS785UM1Copyright 2007 Cirrus LogicUART1 With HDLC and Modem Control SignalsEP93xx User’s Guide141414CRCZ: CRC zero seed0 - Seed CRC calculation

DS785UM1 14-31Copyright 2007 Cirrus Logic UART1 With HDLC and Modem Control SignalsEP93xx User’s Guide141414Default:0x0000_0000Definition:HDLC Address

14-32 DS785UM1Copyright 2007 Cirrus LogicUART1 With HDLC and Modem Control SignalsEP93xx User’s Guide141414Definition:HDLC Receive Information Buffer

DS785UM1 14-33Copyright 2007 Cirrus Logic UART1 With HDLC and Modem Control SignalsEP93xx User’s Guide141414Address:0x808C_021C - Read/WriteDefault:0x

14-34 DS785UM1Copyright 2007 Cirrus LogicUART1 With HDLC and Modem Control SignalsEP93xx User’s Guide141414TBY: Transmitter Busy. (Read Only)0 - TX is

DS785UM1 14-35Copyright 2007 Cirrus Logic UART1 With HDLC and Modem Control SignalsEP93xx User’s Guide141414RFS: Receive FIFO Service request. (Read O

14-36 DS785UM1Copyright 2007 Cirrus LogicUART1 With HDLC and Modem Control SignalsEP93xx User’s Guide141414

DS785UM1 15-1Copyright 2007 Cirrus Logic 151515Chapter 1515UART2 15.1 IntroductionUART2 implements a UART interface identical to that of UART1. UART2

2-18 DS785UM1Copyright 2007 Cirrus LogicARM920T Core and Advanced High-Speed Bus (AHB)EP93xx User’s Guide2220x8000_0140 - 0x8000_017C M2M Channel 1 Re

15-2 DS785UM1Copyright 2007 Cirrus LogicUART2EP93xx User’s Guide151515 Figure 15-1. IrDA SIR Encoder/decoder Block Diagram 15.2.1.1 IrDA SIR Transmit

DS785UM1 15-3Copyright 2007 Cirrus Logic UART2EP93xx User’s Guide151515A start bit is detected when the decoder input is LOW.Regardless of being in no

15-4 DS785UM1Copyright 2007 Cirrus LogicUART2EP93xx User’s Guide151515 15.2.2.1 System/diagnostic Loopback TestingIt is possible to perform loopback t

DS785UM1 15-5Copyright 2007 Cirrus Logic UART2EP93xx User’s Guide151515 15.2.4 Enabling Infrared (Ir) Modes 15.3 UART2 Package DependencyUART2 uses pa

15-6 DS785UM1Copyright 2007 Cirrus LogicUART2EP93xx User’s Guide151515Fuartclk <= 4 x FpclkIf the IrDA SIR functionality is required, UARTCLK must

DS785UM1 15-7Copyright 2007 Cirrus Logic UART2EP93xx User’s Guide151515 15.4 RegistersRegister DescriptionsUART2Data Address:0x808D_0000 - Read/WriteD

15-8 DS785UM1Copyright 2007 Cirrus LogicUART2EP93xx User’s Guide151515UART2RXSts Address:0x808D_0004 - Read/WriteDefault:0x0000_0000Definition:UART Re

DS785UM1 15-9Copyright 2007 Cirrus Logic UART2EP93xx User’s Guide151515FE: Framing Error. When this bit is set to “1”, it indicates that the received

15-10 DS785UM1Copyright 2007 Cirrus LogicUART2EP93xx User’s Guide151515FEN: FIFO Enable. 1 - Transmit and receive FIFO buffers are enabled (FIFO mode)

DS785UM1 15-11Copyright 2007 Cirrus Logic UART2EP93xx User’s Guide151515Definition:UART Line Control Register Middle.Bit Descriptions:RSVD: Reserved.

DS785UM1 2-19Copyright 2007 Cirrus Logic ARM920T Core and Advanced High-Speed Bus (AHB)EP93xx User’s Guide2220x8001_0090 RXDQBAdd MAC Receive Descript

15-12 DS785UM1Copyright 2007 Cirrus LogicUART2EP93xx User’s Guide151515UART2Ctrl Address:0x808D_0014 - Read/WriteDefault:0x0000_0000Definition:UART Co

DS785UM1 15-13Copyright 2007 Cirrus Logic UART2EP93xx User’s Guide151515SIRLP: SIR Low Power Mode. This bit selects the IrDA encoding mode. If this bi

15-14 DS785UM1Copyright 2007 Cirrus LogicUART2EP93xx User’s Guide151515RXFF: Receive FIFO Full. The meaning of this bit depends on the state of the FE

DS785UM1 15-15Copyright 2007 Cirrus Logic UART2EP93xx User’s Guide151515Default:0x0000_0000Definition:UART Interrupt Identification and Interrupt Clea

15-16 DS785UM1Copyright 2007 Cirrus LogicUART2EP93xx User’s Guide151515ILPDV: IrDA Low Power Divisor bits [7:0]. 8-bit low-power divisor value. These

DS785UM1 15-17Copyright 2007 Cirrus Logic UART2EP93xx User’s Guide151515UART2TMR Address:0x808D_0084 - Read/WriteDefault:0x0000_0000Definition:UART SI

15-18 DS785UM1Copyright 2007 Cirrus LogicUART2EP93xx User’s Guide151515.

DS785UM1 16-1Copyright 2007 Cirrus Logic 161616Chapter 1616UART3 With HDLC Encoder 16.1 IntroductionNote: This chapter applies only to the EP9307, EP9

16-2 DS785UM1Copyright 2007 Cirrus LogicUART3 With HDLC EncoderEP93xx User’s Guide161616 16.2.2 Clocking RequirementsThere are two clocks, PCLK and UA

DS785UM1 16-3Copyright 2007 Cirrus Logic UART3 With HDLC EncoderEP93xx User’s Guide161616As another example, assume 230,400 baud (the maximum with a U

2-20 DS785UM1Copyright 2007 Cirrus LogicARM920T Core and Advanced High-Speed Bus (AHB)EP93xx User’s Guide2220x8002_0030 HcDoneHead USB Host Controlle

16-4 DS785UM1Copyright 2007 Cirrus LogicUART3 With HDLC EncoderEP93xx User’s Guide161616a 3-bit status (break, frame and parity) is pushed onto the 11

DS785UM1 16-5Copyright 2007 Cirrus Logic UART3 With HDLC EncoderEP93xx User’s Guide161616BE: Break Error. This bit is set to 1 if a break condition wa

16-6 DS785UM1Copyright 2007 Cirrus LogicUART3 With HDLC EncoderEP93xx User’s Guide161616• UART3LinCtrlMid write, UART3LinCtrlLow write and UART3LinCtr

DS785UM1 16-7Copyright 2007 Cirrus Logic UART3 With HDLC EncoderEP93xx User’s Guide161616UART3LinCtrlMid Address:0x808E_000C - Read/WriteDefault:0x000

16-8 DS785UM1Copyright 2007 Cirrus LogicUART3 With HDLC EncoderEP93xx User’s Guide161616BR: Baud Rate Divisor bits [7:0]. Least significant byte of ba

DS785UM1 16-9Copyright 2007 Cirrus Logic UART3 With HDLC EncoderEP93xx User’s Guide161616UART3Flag Address:0x808E_0018 - Read/WriteDefault:0x0000_0000

16-10 DS785UM1Copyright 2007 Cirrus LogicUART3 With HDLC EncoderEP93xx User’s Guide161616BUSY: UART Busy. If this bit is set to 1, the UART is busy tr

DS785UM1 16-11Copyright 2007 Cirrus Logic UART3 With HDLC EncoderEP93xx User’s Guide161616TIS: Transmit Interrupt Status. This bit is set to 1 if the

16-12 DS785UM1Copyright 2007 Cirrus LogicUART3 With HDLC EncoderEP93xx User’s Guide161616Default:0x0000_0000Definition:UART3 DMA Control RegisterBit D

DS785UM1 16-13Copyright 2007 Cirrus Logic UART3 With HDLC EncoderEP93xx User’s Guide1616160: Must be written as “0”.UART3HDLCCtrl Address:0x808E_020C

DS785UM1 2-21Copyright 2007 Cirrus Logic ARM920T Core and Advanced High-Speed Bus (AHB)EP93xx User’s Guide2220x8003_006C CursorColor1 Cursor color ove

16-14 DS785UM1Copyright 2007 Cirrus LogicUART3 With HDLC EncoderEP93xx User’s Guide161616RXENC: Receive Encoding method. 1 - Use Manchester bit encodi

DS785UM1 16-15Copyright 2007 Cirrus Logic UART3 With HDLC EncoderEP93xx User’s Guide161616CRCApd: CRC pass through.0 - Do not pass received CRC to CPU

16-16 DS785UM1Copyright 2007 Cirrus LogicUART3 With HDLC EncoderEP93xx User’s Guide161616UART3HDLCAddMtchVal Address:0x808E_0210 - Read/WriteDefault:0

DS785UM1 16-17Copyright 2007 Cirrus Logic UART3 With HDLC EncoderEP93xx User’s Guide161616UART3HDLCRXInfoBuf Address:0x808E_0218 - Read/WriteDefault:0

16-18 DS785UM1Copyright 2007 Cirrus LogicUART3 With HDLC EncoderEP93xx User’s Guide161616UART3HDLCSts Address:0x808E_021C - Read/WriteDefault:0x0000_0

DS785UM1 16-19Copyright 2007 Cirrus Logic UART3 With HDLC EncoderEP93xx User’s Guide161616RAB: Receiver Abort. (Read Only)0 - No abort has been detect

16-20 DS785UM1Copyright 2007 Cirrus LogicUART3 With HDLC EncoderEP93xx User’s Guide161616TAB: Transmitted Frame Aborted. (Read/Write)Set “1” when a tr

DS785UM1 17-1Copyright 2007 Cirrus Logic 171717Chapter 1717IrDA 17.1 IntroductionThis module implements the physical layer of an infrared serial port

17-2 DS785UM1Copyright 2007 Cirrus LogicIrDAEP93xx User’s Guide171717 17.3 Shared IrDA Interface FeatureThis section describes features common to the

DS785UM1 17-3Copyright 2007 Cirrus Logic IrDAEP93xx User’s Guide171717 17.3.2.1 General Configuration 17.3.2.1.1 Select Ir ModeThe IrEnable register

vi ©Copyright 2007 Cirrus Logic, Inc. DS785UM1 EP93xx User’s Guide 7.4.8.6 FRAME_CNTx timing ...

2-22 DS785UM1Copyright 2007 Cirrus LogicARM920T Core and Advanced High-Speed Bus (AHB)EP93xx User’s Guide2220x8008_0008 SMCBCR2Bank config Register 2

17-4 DS785UM1Copyright 2007 Cirrus LogicIrDAEP93xx User’s Guide171717 17.3.2.2.2 The Transmit ProcessThis section describes the transmission process

DS785UM1 17-5Copyright 2007 Cirrus Logic IrDAEP93xx User’s Guide171717 17.3.2.2.3 Sending Packets Which are Not a Multiple of 4 Bytes In LengthThe tr

17-6 DS785UM1Copyright 2007 Cirrus LogicIrDAEP93xx User’s Guide171717Set up DMA Set up a DMA buffer (the buffer should be greater than twice the maxim

DS785UM1 17-7Copyright 2007 Cirrus Logic IrDAEP93xx User’s Guide171717The data word and flags are held in the 39-bit wide receiver FIFO. Reading an Ir

17-8 DS785UM1Copyright 2007 Cirrus LogicIrDAEP93xx User’s Guide171717 17.3.3 Control Information BufferingThe ARM Core needs several items of informat

DS785UM1 17-9Copyright 2007 Cirrus Logic IrDAEP93xx User’s Guide171717 Figure 17-1. RZ1/NRZ Bit Encoding Example 17.4.1.2 Frame FormatMIR uses a flag

17-10 DS785UM1Copyright 2007 Cirrus LogicIrDAEP93xx User’s Guide171717 17.4.1.2.1 Address FieldThe 8 bit address field is used by a transmitter to ta

DS785UM1 17-11Copyright 2007 Cirrus Logic IrDAEP93xx User’s Guide171717 17.4.2 Functional DescriptionFollowing reset, the MIR is disabled. Reset also

17-12 DS785UM1Copyright 2007 Cirrus LogicIrDAEP93xx User’s Guide171717receive buffer, ignores the remainder of the frame and begins to search for the

DS785UM1 17-13Copyright 2007 Cirrus Logic IrDAEP93xx User’s Guide171717 17.4.2.3 Transmit OperationImmediately after enabling the MIR for transmission

DS785UM1 2-23Copyright 2007 Cirrus Logic ARM920T Core and Advanced High-Speed Bus (AHB)EP93xx User’s Guide2220x800B_0008 VIC1RawIntr Raw interrupt sta

17-14 DS785UM1Copyright 2007 Cirrus LogicIrDAEP93xx User’s Guide171717 17.5.1 Introduction 17.5.1.1 4PPM ModulationFour position pulse modulation (4PP

DS785UM1 17-15Copyright 2007 Cirrus Logic IrDAEP93xx User’s Guide171717 Figure 17-3. 4PPM Modulation Example 17.5.1.2 4.0 Mbps FIR Frame FormatWhen t

17-16 DS785UM1Copyright 2007 Cirrus LogicIrDAEP93xx User’s Guide171717The preamble, start and stop flags are a mixture of symbols which contain either

DS785UM1 17-17Copyright 2007 Cirrus Logic IrDAEP93xx User’s Guide171717signalled. The CRC computation logic is preset to all ones before reception/tra

17-18 DS785UM1Copyright 2007 Cirrus LogicIrDAEP93xx User’s Guide171717 17.5.2.2 Receive OperationThe IrDA standard specifies that all transmission occ

DS785UM1 17-19Copyright 2007 Cirrus Logic IrDAEP93xx User’s Guide171717When a framing error is detected all subsequent data in the frame is discarded

17-20 DS785UM1Copyright 2007 Cirrus LogicIrDAEP93xx User’s Guide171717When unexpected frame termination is selected and an underrun occurs, the transm

DS785UM1 17-21Copyright 2007 Cirrus Logic IrDAEP93xx User’s Guide171717 17.5.4 IrDA Integration Information 17.5.4.1 Enabling Infrared Modes 17.5.4.2

17-22 DS785UM1Copyright 2007 Cirrus LogicIrDAEP93xx User’s Guide171717To allow sufficient time to write the received data to the receive FIFO, UARTCLK

DS785UM1 17-23Copyright 2007 Cirrus Logic IrDAEP93xx User’s Guide171717 17.6 RegistersRegister DescriptionsIrEnable Address:0x808B_0000 - Read/WriteDe

2-24 DS785UM1Copyright 2007 Cirrus LogicARM920T Core and Advanced High-Speed Bus (AHB)EP93xx User’s Guide2220x800B_0FE8 VIC1PeriphID2 VIC Identificati

17-24 DS785UM1Copyright 2007 Cirrus LogicIrDAEP93xx User’s Guide171717EN: Enable value:00 - No encoder selected01 - SIR, 0 to 0.1152Mbit/s data rate,

DS785UM1 17-25Copyright 2007 Cirrus Logic IrDAEP93xx User’s Guide171717TXP: Transmit Polarity Control.0 - Encoded data is not inverted before being pa

17-26 DS785UM1Copyright 2007 Cirrus LogicIrDAEP93xx User’s Guide171717address of all ones are broadcast frames, and are always matched regardless of t

DS785UM1 17-27Copyright 2007 Cirrus Logic IrDAEP93xx User’s Guide171717WST: Width Status.00 - All four bytes in receive buffer are valid.01 - Least si

17-28 DS785UM1Copyright 2007 Cirrus LogicIrDAEP93xx User’s Guide171717Bit Descriptions:DATA: IrDA data word. Values written and sent to the transmit F

DS785UM1 17-29Copyright 2007 Cirrus Logic IrDAEP93xx User’s Guide171717IrRIB Address:0x808B_0020 - Read OnlyDefault:0x0000_0000Definition:IrDA Receive

17-30 DS785UM1Copyright 2007 Cirrus LogicIrDAEP93xx User’s Guide171717BRAB: Buffered Receiver Abort.0 - No abort was detected in the last frame.1 - Th

DS785UM1 17-31Copyright 2007 Cirrus Logic IrDAEP93xx User’s Guide171717DMAERR: RX DMA error handing enable. If 0, the RX DMA interface ignores error c

17-32 DS785UM1Copyright 2007 Cirrus LogicIrDAEP93xx User’s Guide171717MISR Address:0x808B_0080 - Read/WriteDefault:0x0000_0000Definition:MIR Status Re

DS785UM1 17-33Copyright 2007 Cirrus Logic IrDAEP93xx User’s Guide171717RFS: Receive buffer Service Request (read only).0 - Receive buffer is empty or

DS785UM1 2-25Copyright 2007 Cirrus Logic ARM920T Core and Advanced High-Speed Bus (AHB)EP93xx User’s Guide2220x800C_022C VIC2VectCntl11 Vector control

17-34 DS785UM1Copyright 2007 Cirrus LogicIrDAEP93xx User’s Guide171717RFC: RFC mask bit. When high, the MIR RFC status can generate an interrupt.RFS:

DS785UM1 17-35Copyright 2007 Cirrus Logic IrDAEP93xx User’s Guide171717FISR Address:0x808B_0180 - Read/WriteDefault:0x0000_0000Definition:FIR Status R

17-36 DS785UM1Copyright 2007 Cirrus LogicIrDAEP93xx User’s Guide171717RFS: Receive buffer Service Request (read only).0 - Receive buffer is empty or t

DS785UM1 17-37Copyright 2007 Cirrus Logic IrDAEP93xx User’s Guide171717RFC: RFC mask bit. When high, the FIR RFC status can generate an interrupt.RFS:

17-38 DS785UM1Copyright 2007 Cirrus LogicIrDAEP93xx User’s Guide171717

DS785UM1 18-1Copyright 2007 Cirrus Logic 181818Chapter 1818Timers 18.1 IntroductionThe timers are used to control timed events in the system. For exam

18-2 DS785UM1Copyright 2007 Cirrus LogicTimersEP93xx User’s Guide181818 18.1.2.1 Free Running ModeIn free running mode, counters TC1 and TC2 will wrap

DS785UM1 18-3Copyright 2007 Cirrus Logic TimersEP93xx User’s Guide181818Register DescriptionsTimer1Load, Timer2Load Address:Timer1 - 0x8081_0000 -

18-4 DS785UM1Copyright 2007 Cirrus LogicTimersEP93xx User’s Guide181818Definition:The Load register contains the initial value of the timer and is als

DS785UM1 18-5Copyright 2007 Cirrus Logic TimersEP93xx User’s Guide181818Address:Timer3 - 0x8081_0084 - Read OnlyReset Value:0x0000_0000Definition:The

2-26 DS785UM1Copyright 2007 Cirrus LogicARM920T Core and Advanced High-Speed Bus (AHB)EP93xx User’s Guide2220x8082_003C I2STX2En TX2 Channel Enable N0

18-6 DS785UM1Copyright 2007 Cirrus LogicTimersEP93xx User’s Guide181818Timer1Control, Timer2Control, Timer3Control Address:Timer1 - 0x8081_0008 - R

DS785UM1 18-7Copyright 2007 Cirrus Logic TimersEP93xx User’s Guide181818Timer4ValueLowAddress:Timer4 - 0x8081_0060 - Read OnlyReset Value:0x0000_0000D

18-8 DS785UM1Copyright 2007 Cirrus LogicTimersEP93xx User’s Guide181818Bit Descriptions:RSVD: Reserved. Unknown during a Read operation. Enable: Read/

DS785UM1 19-1Copyright 2007 Cirrus Logic 191919Chapter 1919Watchdog Timer 19.1 IntroductionThe Watchdog Timer provides a mechanism for generating a sy

19-2 DS785UM1Copyright 2007 Cirrus LogicWatchdog TimerEP93xx User’s Guide191919 19.1.1 Watchdog ActivationThe Watchdog circuitry may be disabled via s

DS785UM1 19-3Copyright 2007 Cirrus Logic Watchdog TimerEP93xx User’s Guide191919Note: A software reset can reset the system without this register losi

19-4 DS785UM1Copyright 2007 Cirrus LogicWatchdog TimerEP93xx User’s Guide191919READ ONLY BIT FIELDSPLSDSN: Pulse Disable Not. The Watchdog internal PL

DS785UM1 19-5Copyright 2007 Cirrus Logic Watchdog TimerEP93xx User’s Guide191919WDStatusAddress:0x8094_0004 - Read/WriteDefault:0x0000_0000Definition:

19-6 DS785UM1Copyright 2007 Cirrus LogicWatchdog TimerEP93xx User’s Guide191919

DS785UM1 20-1Copyright 2007 Cirrus Logic 202020Chapter 2020Real Time Clock With Software Trim 20.1 IntroductionThe Real Time Clock (RTC) is a circuit

DS785UM1 2-27Copyright 2007 Cirrus Logic ARM920T Core and Advanced High-Speed Bus (AHB)EP93xx User’s Guide2220x8084_005C IntStsFGPIO Interrupt Status

20-2 DS785UM1Copyright 2007 Cirrus LogicReal Time Clock With Software TrimEP93xx User’s Guide202020 20.1.1.1 Software CompensationThe 1 Hz clock is ge

DS785UM1 20-3Copyright 2007 Cirrus Logic Real Time Clock With Software TrimEP93xx User’s Guide202020 20.1.1.4 Example - Measured Value Split Into Inte

20-4 DS785UM1Copyright 2007 Cirrus LogicReal Time Clock With Software TrimEP93xx User’s Guide202020 20.1.2 Reset ControlThe RTC block level reset oper

DS785UM1 20-5Copyright 2007 Cirrus Logic Real Time Clock With Software TrimEP93xx User’s Guide202020RTCMatch Address:0x8092_0004 - Read/WriteDefault:0

20-6 DS785UM1Copyright 2007 Cirrus LogicReal Time Clock With Software TrimEP93xx User’s Guide202020RTCLoad Address:0x8092_000C - Read/WriteDefault:0x0

DS785UM1 20-7Copyright 2007 Cirrus Logic Real Time Clock With Software TrimEP93xx User’s Guide202020RTCSWComp Address:0x8092_0108 - Read/WriteDefault:

20-8 DS785UM1Copyright 2007 Cirrus LogicReal Time Clock With Software TrimEP93xx User’s Guide202020

DS785UM1 21-1Copyright 2007 Cirrus Logic 212121Chapter 2121I2S Controller 21.1 IntroductionThe I2S controller is used to stream serial audio data betw

21-2 DS785UM1Copyright 2007 Cirrus LogicI2S ControllerEP93xx User’s Guide212121The primary I2S port and the I2S clocks are multiplexed and can be assi

DS785UM1 21-3Copyright 2007 Cirrus Logic I2S ControllerEP93xx User’s Guide212121• Supports 16/24/32 bit word lengths.• Programmable left/right word cl

2-28 DS785UM1Copyright 2007 Cirrus LogicARM920T Core and Advanced High-Speed Bus (AHB)EP93xx User’s Guide2220x8088_0034 AC97ISR2 Interrupt Status N0x8

21-4 DS785UM1Copyright 2007 Cirrus LogicI2S ControllerEP93xx User’s Guide212121these two words will occupy positions 0 and 1 in the FIFO. The FIFO now

DS785UM1 21-5Copyright 2007 Cirrus Logic I2S ControllerEP93xx User’s Guide212121The I2S transmit and receive channels should be disabled before change

21-6 DS785UM1Copyright 2007 Cirrus LogicI2S ControllerEP93xx User’s Guide212121• Programmable first data bit position. that is, I2S or non-I2S format.

DS785UM1 21-7Copyright 2007 Cirrus Logic I2S ControllerEP93xx User’s Guide212121Descriptions” on page 448.) Note that both left and right sample regis

21-8 DS785UM1Copyright 2007 Cirrus LogicI2S ControllerEP93xx User’s Guide212121order to generate a set of audio clocks, LRCK (word clock) and SCLK (bi

DS785UM1 21-9Copyright 2007 Cirrus Logic I2S ControllerEP93xx User’s Guide212121 21.5 I2S Bit Clock Rate Generation 21.5.1 Example of the Bit Cloc

21-10 DS785UM1Copyright 2007 Cirrus LogicI2S ControllerEP93xx User’s Guide212121 Figure 21-2. Bit Clock Generation Example 21.5.2 Example of Rig

DS785UM1 21-11Copyright 2007 Cirrus Logic I2S ControllerEP93xx User’s Guide212121• TX2 FIFO empty.• TX underflow.The first three can have their interr

21-12 DS785UM1Copyright 2007 Cirrus LogicI2S ControllerEP93xx User’s Guide212121 21.7 Registers 21.7.1 I2S TX RegistersTable 21-7 summarizes the regis

DS785UM1 21-13Copyright 2007 Cirrus Logic I2S ControllerEP93xx User’s Guide212121I2S TX Register Descriptions I2STX0Lft Address:0x8082_0010 - Re

DS785UM1 2-29Copyright 2007 Cirrus Logic ARM920T Core and Advanced High-Speed Bus (AHB)EP93xx User’s Guide2220x808B_0008 IrAdrMatchVal IrDA Address Ma

21-14 DS785UM1Copyright 2007 Cirrus LogicI2S ControllerEP93xx User’s Guide212121I2STX1Lft Address:0x8082_0018 - Read/WriteDefault:0x0000_0000Defini

DS785UM1 21-15Copyright 2007 Cirrus Logic I2S ControllerEP93xx User’s Guide212121I2STX2Lft Address:0x8082_0020 - Read/WriteDefault:0x0000_0000Defi