Cirrus-logic CS5345 Uživatelský manuál

Copyright  Cirrus Logic, Inc. 2012(All Rights Reserved)http://www.cirrus.com104 dB, 24-Bit, 192 kHz Stereo Audio ADCA/D Features Multi-Bit Delta Sig

10 DS658F4CS5345ADC ANALOG CHARACTERISTICS (Continued) 5. Referred to the typical line-level full-scale input voltage6. Valid for Double- and Quad

DS658F4 11CS5345ADC DIGITAL FILTER CHARACTERISTICS 8. Filter response is guaranteed by design.9. Response shown is for Fs = 48 kHz. 10. Respon

12 DS658F4CS5345PGAOUT ANALOG CHARACTERISTICS Test conditions (unless otherwise specified): AGND = DGND = 0 V; VA = 3.13 V to 5.25 V; VD = 3.13 V to 5

DS658F4 13CS5345PGAOUT ANALOG CHARACTERISTICS (Continued)VA = 3.13 V to 3.46 VParameter Symbol Min Typ Max UnitDynamic Performance with PGA Line-Level

14 DS658F4CS5345PGAOUT ANALOG CHARACTERISTICS (Continued) 12. Guaranteed by design.VA = 3.13 V to 5.25 VParameter Symbol Min Typ Max UnitDC Accuracy w

DS658F4 15CS5345DC ELECTRICAL CHARACTERISTICSAGND = DGND = 0 V, all voltages with respect to ground. MCLK=12.288 MHz; Fs=48 kHz; Master Mode.13. Power

16 DS658F4CS5345DIGITAL INTERFACE CHARACTERISTICSTest conditions (unless otherwise specified): AGND = DGND = 0 V; VLS = VLC = 1.71 V to 5.25 V.16. Ser

DS658F4 17CS5345SWITCHING CHARACTERISTICS - SERIAL AUDIO PORTLogic ‘0’ = DGND = AGND = 0 V; Logic ‘1’ = VL, CL = 20 pF. (Note 18)18. See Figure 1 and

18 DS658F4CS5345 slrtSDOUTSCLKOutputLRCKOutputsdotslrtSDOUTSCLKInputLRCKInputsdotsclkhtsclkltsclkwtFigure 1. Master Mode Serial Audio

DS658F4 19CS5345 Figure 3. Format 0, Left-Justified up to 24-Bit DataLRCKSCLK SDATA+3 +2 +1+5 +4-1 -2 -3 -4 -5+3 +2 +1+5 +4MSB-1 -2 -3 -4Channel A -

2 DS658F4CS5345TABLE OF CONTENTS1. PIN DESCRIPTIONS ...

20 DS658F4CS5345SWITCHING CHARACTERISTICS - CONTROL PORT - I²C FORMATInputs: Logic 0 = DGND = AGND = 0 V, Logic 1 = VLC, CL=30pF.19. Data must be held

DS658F4 21CS5345SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT Inputs: Logic 0 = DGND = AGND = 0 V, Logic 1 = VLC, CL=30pF.21. Data must be hel

22 DS658F4CS53453. TYPICAL CONNECTION DIAGRAMVLS0.1 µF+1.8Vto +5VDGNDVLC0.1 µF+1.8Vto +5VSCL/CCLKSDA/CDOUTAD1/CDINRESET2 kSee Note 1AGNDAD0/CSNote 1:

DS658F4 23CS53454. APPLICATIONS4.1 Recommended Power-Up Sequence1. Hold RESET low until the power supply, MCLK, and LRCK are stable. In this state, th

24 DS658F4CS5345In both Master and Slave Modes, the external MCLK must be divided down based on the MCLK/LRCK ratio to achieve a post-divider MCLK/LRC

DS658F4 25CS5345which could result in recording a DC level, possibly yielding clicks when switching between devices in a mul-tichannel system.The high

26 DS658F4CS53454.4 Analog Input Multiplexer, PGA, and Mic GainThe CS5345 contains a stereo 6-to-1 analog input multiplexer followed by a programmable

DS658F4 27CS53454.7 Control Port Description and TimingThe control port is used to access the registers, allowing the CS5345 to be configured for the

28 DS658F4CS5345be connected through a resistor to VLC or DGND as desired. The state of the pins is sensed while the CS5345 is being reset. The signal

DS658F4 29CS5345Receive byte, contents of selected register. Send acknowledge bit. Send stop condition. 4.8 Interrupts and OverflowThe CS5345 has a co

DS658F4 3CS53456.6.1 Channel B PGA Gain (Bits 5:0) ... 346.7

30 DS658F4CS5345system logic supply (VLS or VLC) or may be powered from the analog supply (VA) via a resistor. In thiscase, no additional devices shou

DS658F4 31CS53455. REGISTER QUICK REFERENCEThis table shows the register names and their associated default values.Addr Function 7 6 5 4 3 2 1 001h Ch

32 DS658F4CS53456. REGISTER DESCRIPTION6.1 Chip ID - Register 01hFunction:This register is Read-Only. Bits 7 through 4 are the part number ID, which i

DS658F4 33CS53456.3 ADC Control - Address 04h6.3.1 Functional Mode (Bits 7:6)Function:Selects the required range of sample rates.6.3.2 Digital Interfa

34 DS658F4CS53456.4 MCLK Frequency - Address 05h6.4.1 Master Clock Dividers (Bits 6:4)Function:Sets the frequency of the supplied MCLK signal. See Tab

DS658F4 35CS53456.7 Channel A PGA Control - Address 08h6.7.1 Channel A PGA Gain (Bits 5:0)Function:Sets the gain or attenuation for the ADC input PGA

36 DS658F4CS53456.8.2 Analog Input Selection (Bits 2:0)Function:These bits are used to select the input source for the PGA and ADC. Please see Table 1

DS658F4 37CS53456.10.1 Clock Error (Bit 3)Function:Indicates the occurrence of a clock error condition.6.10.2 Overflow (Bit 1)Function:Indicates the o

38 DS658F4CS53457. PARAMETER DEFINITIONSDynamic RangeThe ratio of the rms value of the signal to the rms sum of all other spectral components over the

DS658F4 39CS53458. FILTER PLOTS Figure 13. Single-Speed Stopband Rejection Figure 14. Single-Speed Stopband RejectionFigure 15. Single-Speed T

4 DS658F4CS5345Table 5. Device Revision ...

40 DS658F4CS5345 Figure 19. Double-Speed Transition Band (Detail) Figure 20. Double-Speed Passband RippleFigure 21. Quad-Speed Stop

DS658F4 41CS53459. PACKAGE DIMENSIONS10.THERMAL CHARACTERISTICS AND SPECIFICATIONS 1. JA is specified according to JEDEC specifications for multi-la

42 DS658F4CS534511.ORDERING INFORMATION 12.REVISION HISTORYProduct Description Package Pb-Free Grade Temp Range Container Order #CS534524-bit, 19

DS658F4 5CS53451. PIN DESCRIPTIONS Pin Name # Pin DescriptionSDA/CDOUT 1Serial Control Data (Input/Output) - SDA is a data I/O in I²C® Mode. CDOUT

6 DS658F4CS5345AIN1AAIN1B1112Stereo Analog Input 1 (Input) - The full-scale level is specified in the ADC Analog Characteristics specification table.A

DS658F4 7CS53452. CHARACTERISTICS AND SPECIFICATIONSSPECIFIED OPERATING CONDITIONSAGND = DGND = 0 V; All voltages with respect to ground.Notes: 1. Max

8 DS658F4CS5345ADC ANALOG CHARACTERISTICS Test conditions (unless otherwise specified): AGND = DGND = 0 V; VA = 3.13 V to 5.25 V; VD = 3.13 V to 5.25

DS658F4 9CS53454. Valid for the selected input pair.DC AccuracyGain Error --10 %Gain Drift -100 - ppm/°CLine-Level Input CharacteristicsFull-scale I