Cirrus-logic CS8416 Uživatelský manuál stáhnout pdf (Strana 55)

DS578F3 55

CS8416

18.2.5 Jitter Attenuation

Shown in Figure 25 is the jitter attenuation plot. The AES3 and IEC60958-4 specifications state a maxi-

mum of 2 dB jitter gain or peaking.

J itte r F re que ncy (H z )

externa l J itte r Attenuation ( dB )

Figure 25. Jitter Attenuation Characteristics of PLL

1 2 ... 50 51 52 53 54 55 56 57 58 59 60

Features 1
General Description 2
TABLE OF CONTENTS 3
LIST OF FIGURES 5
LIST OF TABLES 5
ABSOLUTE MAXIMUM RATINGS 6
DIGITAL INPUT CHARACTERISTICS 7
SWITCHING CHARACTERISTICS 8
10 DS578F3 10
Parameter Symbol Min Max Unit 10
Figure 3. SPI Mode Timing 10
DS578F3 11 11
Figure 4. I²C Mode Timing 11
2.1 TSSOP Pin Description 12
DS578F3 13 13
Pin # Pin Description 13
2.2 QFN Pin Description 14
DS578F3 15 15
3.1 TSSOP Pin Description 16
DS578F3 17 17
3.2 QFN Pin Description 18
DS578F3 19 19
20 DS578F3 20
DS578F3 21 21
Ω resistor 21
5. APPLICATIONS 22
6. GENERAL DESCRIPTION 23
7. SERIAL AUDIO OUTPUT PORT 23
24 DS578F3 24
7.1 Slip/Repeat Behavior 25
7.2 AES11 Behavior 26
8. S/PDIF RECEIVER 27
8.1.3 Hardware Mode 28
8.2 OMCK System Clock Mode 28
9. GENERAL PURPOSE OUTPUTS 29
10.ERROR AND STATUS REPORTING 30
10.2 Non-Audio Detection 31
10.2.1 Format Detection 31
10.3 Interrupts 31
11.1 Software Mode 32
11.2 Hardware Mode 32
12.CONTROL PORT DESCRIPTION 33
12.2 I²C Mode 34
DS578F3 35 35
R/WFunction76543210 35
14.2 Control0 (00h) 36
14.3 Control1 (01h) 37
14.4 Control2 (02h) 38
14.5 Control3 (03h) 39
14.6 Control4 (04h) 39
76543210 40
14.9 Interrupt Mask (07h) 41
14.13 Receiver Error (0Ch) 43
15.HARDWARE MODE 46
50 DS578F3 50
17.2 Accessing the E Buffer 51
D to E interrupt occurs 52
Optionally set D to E inhibit 52
Read E data 52
If set, clear D to E inhibit 52
18.PLL FILTER 53
18.2.2 Capacitor Selection 54
18.2.3 Circuit Board Layout 54
18.2.5 Jitter Attenuation 55
19.PACKAGE DIMENSIONS 56
TSSOP THERMAL CHARACTERISTICS 57
QFN THERMAL CHARACTERISTICS 58
20.ORDERING INFORMATION 59
21.REVISION HISTORY 60

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