Cirrus-logic CS5480 Uživatelský manuál

Copyright  Cirrus Logic, Inc. 2013(All Rights Reserved)Cirrus Logic, Inc.http://www.cirrus.comCS5480Three Channel Energy Measurement ICFeatures• Supe

CS548010 DS980F3-1-0.500.510 500 1000 1500 2000 2500 3000 3500 4000 4500Percent Error (%)Current Dynamic Range (x : 1)Lagging sin(੮) = 0.5Leading sin(

CS5480DS980F3 11ANALOG CHARACTERISTICS• Min / Max characteristics and specifications are guaranteed over all Recommended Operating Conditions.• Typica

CS548012 DS980F3Notes: 5. All outputs unloaded. All inputs CMOS level.6. Temperature accuracy measured after calibration is performed.7. Measurement m

CS5480DS980F3 13DIGITAL CHARACTERISTICS• Min / Max characteristics and specifications are guaranteed over all Recommended Operating Conditions.• Typic

CS548014 DS980F3SWITCHING CHARACTERISTICS• Min / Max characteristics and specifications are guaranteed over all Recommended Operating Conditions.• Typ

CS5480DS980F3 15 SDOSDIt1t2t3t4t5t6t7t8CSSCLKMSBMSB MSB-1MSB-1INTERMEDIATE BITSINTERMEDIATE BITSLSBLSBFigure 7. SPI Data and Clock TimingTXRXt9t11CSS

CS548016 DS980F3ABSOLUTE MAXIMUM RATINGSNotes: 16. VDDA and GNDA must satisfy [(VDDA) – (GNDA)]  + 4.0V.17. Applies to all pins, including continuous

CS5480DS980F3 174. SIGNAL FLOW DESCRIPTIONThe signal flow for voltage measurement, currentmeasurement, and the other calculations is shown inFigures 9

CS548018 DS980F34.4 Phase CompensationPhase compensation changes the phase of voltagerelative to current by adding a delay in the decimationfilters.

CS5480DS980F3 194.8.1 Fixed Number of Samples AveragingN is the preset value in the SampleCount register andshould not be set less than 100. By defau

CS54802 DS980F3TABLE OF CONTENTS1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CS548020 DS980F3These offsets can be either positive or negative,indicating crosstalk coupling either in phase or out ofphase with the applied voltage

CS5480DS980F3 215. FUNCTIONAL DESCRIPTION5.1 Power-on ResetThe CS5480 has an internal power supply supervisorcircuit that monitors the VDDA and VDDD

CS548022 DS980F35.4 Line Frequency Measurement If the Automatic Frequency Calculation (AFC) bit in theConfig2 register is set, the line frequency mea

CS5480DS980F3 235.5 Meter Configuration ModesThere are two distinct meter configuration modes in theCS5480 that affect how the total active, reactive

CS548024 DS980F35.6 Tamper Detection and CorrectionIn the 1V-1I-1N meter configuration mode, the CS5480provides flexibility for the user and applicat

CS5480DS980F3 255.6.1.2 Manual Channel SelectionIn addition to automatic channel selection anti-tamper-ing scheme, the CS5480 allows the user or appl

CS548026 DS980F3After reset, all three energy pulse generation blocks aredisabled (DOxMODE[3:0] = Hi-Z). To output a desiredenergy pulse to a DOx pin,

CS5480DS980F3 275.9 Phase Sequence DetectionPolyphase meters using multiple CS5480 devices maybe configured to sense the succession of voltagezero-cr

CS548028 DS980F3The application program can change both the scale andrange of temperature by changing the TemperatureGain (TGAIN) and Temperature Offs

CS5480DS980F3 296. HOST COMMANDS AND REGISTERS6.1 Host CommandsThe first byte sent to the CS5480 SDI/RX pin containsthe host command. Four types of h

CS5480DS980F3 35.7.1 Pulse Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265.7.2 Pulse Wi

CS548030 DS980F36.1.3 ChecksumTo improve the communication reliability on the serialinterface, the CS5480 provides a checksum mechanismon transmitted

CS5480DS980F3 316.2 Hardware Registers Summary (Page 0)Address2RA[5:0] Name Description1DSP3HOST3Default0* 00 0000 Config0 Configuration 0 Y Y 0x C0

CS548032 DS980F351 11 0011 - Reserved -52 11 0100 - Reserved -53 11 0101 - Reserved -54 11 0110 - Reserved -55 11 0111 ZXNUMNum. Zero Crosses used fo

CS5480DS980F3 336.3 Software Registers Summary (Page 16)Address2RA[5:0] Name Description1DSP3HOST3Default0* 00 0000 Config2 Configuration 2 Y Y 0x 00

CS548034 DS980F351** 11 0011 SampleCount Sample Count N Y 0x 00 0FA052 11 0100 - Reserved -53 11 0101 - Reserved -54* 11 0110 TGAINTemperature Gain Y

CS5480DS980F3 356.4 Software Registers Summary (Page 17)Address2RA[5:0] Name Description1DSP3HOST3Default0* 00 0000 V1SagDURV1 Sag Duration Y Y 0x 00

CS548036 DS980F36.5 Software Registers Summary (Page 18)Address2RA[5:0] Name Description1DSP3HOST3Default24* 01 1000 IZXLEVELZero-Cross Threshold for

CS5480DS980F3 376.6 Register Descriptions22. “Default” = bit states after power-on or reset23. DO NOT write a “1” to any unpublished register bit or

CS548038 DS980F36.6.2 Configuration 1 (Config1) – Page 0, Address 1 Default = 0x00 EEEE[23] Reserved.EPG3_ON Enable EPG3 block.0 = Disable energy pul

CS5480DS980F3 39DO2MODE[3:0] Output control for DO2 pin.0000 = Energy pulse generation block 1 (EPG1) output0001 = Energy pulse generation block 2 (EP

CS54804 DS980F3LIST OF FIGURESFigure 1. Oscillator Connections...

CS548040 DS980F36.6.3 Configuration 2 (Config2) – Page 16, Address 0 Default = 0x00 0200VFIX Use internal RMS voltage reference instead of voltage

CS5480DS980F3 41REG_CSUM_OFF Disable checksum on critical registers.0 = Enable checksum on critical registers (Default)1 = Disable checksum on critica

CS548042 DS980F36.6.4 Phase Compensation (PC) – Page 0, Address 5 Default = 0x00 0000CPCC2[1:0] Coarse phase compensation control for I2 and V2.00 =

CS5480DS980F3 436.6.6 Pulse Output Width (PulseWidth) – Page 0, Address 8Default = 0x00 0001 (265.6µs at OWR = 4kHz)PulseWidth sets the energy pulse

CS548044 DS980F36.6.9 Pulse Output Control (PulseCtrl) – Page 0, Address 9 Default = 0x00 0000This register controls the input to the energy pulse ge

CS5480DS980F3 456.6.11 Phase Sequence Detection and Control (PSDC) – Page 0, Address 48 Default = 0x00 0000DONE Indicates valid count values reside i

CS548046 DS980F36.6.13 Interrupt Status (Status0) – Page 0, Address 23Default = 0x80 0000The Status0 register indicates a variety of conditions withi

CS5480DS980F3 476.6.14 Interrupt Mask (Mask) – Page 0, Address 3 Default = 0x00 0000The Mask register is used to control the activation of the INT p

CS548048 DS980F36.6.16 Chip Status 2 (Status2) – Page 0, Address 25Default = 0x00 0000This register indicates a variety of conditions within the chip

CS5480DS980F3 496.6.18 Automatic Channel Select Level (IchanLEVEL ) – Page 16, Address 50Default = 0x82 8F5C (1.02 or 2% minimum difference)Sets the

CS5480DS980F3 51. OVERVIEWThe CS5480 is a CMOS power measurement integrated circuit that uses three  analog-to-digitalconverters to measure line vol

CS548050 DS980F36.6.21 Voltage Fixed RMS Reference (VFRMS) – Page 16, Address 59 Default = 0x5A 8279 (0.7071068)The VFRMS register contains the inter

CS5480DS980F3 516.6.25 System Gain (SysGAIN) – Page 16, Address 60 Default = 0x50 0000 (1.25)System Gain (SysGAIN) is applied to all channels. By def

CS548052 DS980F36.6.29 Voltage 1 Sag Level (V1SagLEVEL) – Page 17, Address 1 Default = 0x00 0000Voltage 1 Sag Level, V1SagLEVEL, establishes a thresh

CS5480DS980F3 536.6.34 Current 2 Overcurrent Duration (I2OverDUR) – Page 17, Address 12 Default = 0x00 0000Current 2 Overcurrent Duration, I2OverDUR,

CS548054 DS980F36.6.39 Voltage 2 Swell Level (V2SwellLEVEL) – Page 18, Address 51 Default = 0x7F FFFFVoltage 2 Swell Level, V2SwellLEVEL, establishes

CS5480DS980F3 556.6.44 RMS Current 1 (I1RMS) – Page 16, Address 6Default = 0x00 0000I1RMS contains the root mean square (RMS) values of I1, calculate

CS548056 DS980F36.6.49 Active Power 2 (P2AVG) – Page 16, Address 11Default = 0x00 0000Instantaneous power is averaged over each low-rate interval (Sa

CS5480DS980F3 576.6.54 Reactive Power 2 (Q2Avg) – Page 16, Address 16Default = 0x00 0000Reactive power 2 (Q2AVG) is Q2 averaged over each low-rate in

CS548058 DS980F36.6.59 Power Factor 1 (PF1) – Page 16, Address 21 Default = 0x00 0000Power factor 1 (PF1) is calculated by dividing active power 1 (P

CS5480DS980F3 596.6.64 Temperature (T) – Page 16, Address 27Default = 0x00 0000T contains results from the on-chip temperature measurement. By defaul

CS54806 DS980F32. PIN DESCRIPTIONClock GeneratorCrystal InCrystal Out1,24XIN, XOUT — Connect to an external quartz crystal. Alternatively, an external

CS548060 DS980F36.6.68 DC Offset for Current (I1DCOFF, I2DCOFF) – Page 16, Address 32, 39Default = 0x00 0000DC offset registers I1DCOFF and I2DCOFF a

CS5480DS980F3 616.6.73 Average Reactive Power Offset (Q1OFF , Q2OFF) – Page 16, Address 38, 45Default = 0x00 0000Average Reactive Power Offset (Q1OFF

CS548062 DS980F36.6.77 Calibration Scale (Scale) – Page18, Address 63Default = 0x4C CCCC (0.6)The Scale register is used in the gain calibration to s

CS5480DS980F3 637. SYSTEM CALIBRATIONComponent tolerances, residual ADC offset, andsystem noise require a meter to be calibrated before itmeets a spec

CS548064 DS980F3The AC offset register for the channel being calibratedshould first be cleared prior to performing thecalibration. The high-pass filte

CS5480DS980F3 656) If the phase offset is negative, then the delay shouldbe added only to the current channel. Otherwise,add more delay to the voltage

CS548066 DS980F38. BASIC APPLICATION CIRCUITSFigure 27 shows the CS5480 configured to measurepower in a single-phase, 3-wire system with 1 voltageand

CS5480DS980F3 675 x 330KCS548027nF27nF1K1KLNIIN1+IIN1-IIN2-IIN2+Application ProcessorRESETRXTXGNDA GNDDDO3DO1DO2VDDA+3.3V0.1µF0.1µF+3 .3VVDDD+3.3VVRE

CS548068 DS980F39. PACKAGE DIMENSIONSmm inchDimension MIN NOM MAX MIN NOM MAXA 0.80 0.90 1.00 0.031 0.035 0.039A1 0.00 0.02 0.05 0.000 0.001 0.002A3

CS5480DS980F3 6910. ORDERING INFORMATION11. ENVIRONMENTAL, MANUFACTURING, AND HANDLING INFORMATION* MSL (Moisture Sensitivity Level) as specified by

CS5480DS980F3 72.1 Analog PinsThe CS5480 has a differential input (VIN) for voltageinput and two differential inputsIIN1 IIN2) forcurrent1 and

CS548070 DS980F3Contacting Cirrus Logic SupportFor all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the one ne

CS54808 DS980F32.2.3.1 SPIThe CS5480 provides a Serial Peripheral Interface(SPI) that operates as a slave device in 4-wire modeand supports multiple

CS5480DS980F3 93. CHARACTERISTICS AND SPECIFICATIONSRECOMMENDED OPERATING CONDITIONSPOWER MEASUREMENT CHARACTERISTICSNotes: 1. Specifications guarante