Cirrus-logic AN118 Uživatelský manuál

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1
Copyright
Cirrus Logic, Inc. 1999
(All Rights Reserved)
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.cirrus.com
AN118
Application Note
Interfacing the CS5521/22/23/24/28 to the 80C51
TABLE OF CONTENTS
1. INTRODUCTION ................................................... 1
2. ADC DIGITAL INTERFACE ................................... 1
3. SOFTWARE DESCRIPTION ................................. 1
3.1 Main Program Loop .......................................... 2
3.2 Initialize ............................................................. 2
3.3 Transfer Data To/From ADC ............................. 3
3.4 Transfer Data To/From PC ............................... 3
3.5 Decoding PC Commands ................................. 5
3.6 Sample Index .................................................... 6
3.7 Test Modes ....................................................... 6
4. MAXIMUM SCLK RATE ......................................... 8
5. DEVELOPMENT TOOL DESCRIPTION ................ 8
6. CONCLUSION ....................................................... 8
7. APPENDIX: 80C51 MICROCONTROLLER CODE 9
1. INTRODUCTION
This application note details the interface of Crys-
tal Semiconductor’s CS5521/22/23/24/28 Analog-
to-Digital Converter (ADC) to an 80C51 micro-
controller. It includes the complete code written for
the CDB5521/22/23/24/28 Evaluation Board,
which also interfaces the 80C51 to a PC. All algo-
rithms discussed are included in Section 7. “Ap-
pendix: 80C51 Microcontroller Code” on page 9.
2. ADC DIGITAL INTERFACE
The CS5521/22/23/24/28 interfaces to the 80C51
through either a three-wire or a four-wire interface.
Figure 1 depicts the interface between the two de-
vices. This software was written to interface to Port
1 (P1) on the 80C51 with either type of interface.
The ADC’s serial port consists of four control
lines: CS, SCLK, SDI, and SDO.
CS, Chip Select, is the control line which enables
access to the serial port.
SCLK, Serial Clock, is the bit-clock which controls
the shifting of data to or from the ADC’s serial
port.
SDI, Serial Data In, is the data signal used to trans-
fer data from the 80C51 to the ADC.
SDO, Serial Data Out, is the data signal used to
transfer output data from the ADC to the 80C51.
3. SOFTWARE DESCRIPTION
This note details all of the algorithms contained in
the CDB5521/22/23/24/28 Evaluation Board soft-
ware. The software is written for the 80C51 micro-
controller on the evaluation board. The more
important communication algorithms are written in
CS5521/22/23/24/28 80C51
P1.0
P1.1
P1.2
P1.3
CS
SDI
SDO
SCLK
Figure 1. 3-Wire and 4-Wire Interfaces
CS5521/22/23/24/28
80C51
P1.0 (logic 0)
P1.1
P1.2
P1.3
CS
SDI
SDO
SCLK
NOV ‘99
AN118REV2
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Strany 1 - Application Note

1Copyright  Cirrus Logic, Inc. 1999(All Rights Reserved)P.O. Box 17847, Austin, Texas 78760(512) 445 7222 FAX: (512) 445 7581http://www.cirrus.comA

Strany 2 - 3.2 Initialize

AN11810 AN118REV2sbit SCLK = 0x93 ; /* Serial Clock */sbit A1 = 0x94 ; /* Latch Input */sbit A0 = 0x95 ; /* Latch Input */sbit RESET = 0x

Strany 3 - 3.4 Transfer Data To/From PC

AN118AN118REV2 11sbit PX1 = 0xBA;sbit PT0 = 0xB9;sbit PX0 = 0xB8;/* P3 */sbit RD = 0xB7;sbit WR = 0xB6;sbit T1 = 0xB5;sbit T0

Strany 4 - Figure 5. Read-Cycle Timing

AN11812 AN118REV2/**************************************************************//* Routine - Main *//* Input - none *//* Output - none

Strany 5 - 3.5 Decoding PC Commands

AN118AN118REV2 13P3 = 0xFF; /*Use the alternative function of Port 3*/EA = 0x00; /*Disable all interrupts*/SCON = 0x72; /*8 bit UAR

Strany 6 - 3.7 Test Modes

AN11814 AN118REV2/**************************************************************//* Routine - read_register *//* Input - command *//* Outpu

Strany 7 - AN118REV2 7

AN118AN118REV2 15case 0x11: /* Offset Register Physical Channel 2 */case 0x21: /* Offset Register Physical Channel 3 */case 0x31: /* Of

Strany 8 - 6. CONCLUSION

AN11816 AN118REV2/**********************//* Read from Register *//**********************/case 0x09: /* Offset Register Physical Channel 1 */case

Strany 9

AN118AN118REV2 17low_byte = receive_byte();TXSER(low_byte); /* Return bytes to PC */TXSER(mid_byte); TXSER(high_byte);}if (temp1

Strany 10

AN11818 AN118REV2case 0xA0: /* Normal Conversion on Setup 5 */case 0xA8: /* Normal Conversion on Setup 6 */case 0xB0: /* Normal Conversion

Strany 11

AN118AN118REV2 19case 0xC2: /* Self-Gain Cal on Setup 9 */case 0xCA: /* Self-Gain Cal on Setup 10 */case 0xD2: /* Self-Gain Cal on Setup 11

Strany 12

AN1182 AN118REV280C51 assembly language, providing a good set oftools for both C and assembly programmers tobuild their own designs upon. While readin

Strany 13

AN11820 AN118REV2case 0xEE: /* System-Gain Cal on Setup 14 */case 0xF6: /* System-Gain Cal on Setup 15 */case 0xFE: /* System-Gain C

Strany 14

AN118AN118REV2 21temp1 = RXSER(); /* Which PC Cal. register is influenced? */decode_sample_index();if(mode == 1) P1 = 0xF4; /* Clear C

Strany 15

AN11822 AN118REV2write_to_register(0x03,0x00,0x00,0x00); /* Clear RS Bit */ } while (temp != 0x40);break;/**********************//* Read Output Latch

Strany 16

AN118AN118REV2 23/********************************//* No Cases were met, let port time out *//********************************/default:break;}}/* END

Strany 17

AN11824 AN118REV2sample_size = 1;break; default:sample_size = 0;break;}} /* END decode_sample_index *//**********************************************

Strany 18

AN118AN118REV2 25elsetoggle_two_leds(); /* Test Failed */break;/* Test Mode 3: This test lights the first two LED and thenrepeatively iniates a conver

Strany 19

AN11826 AN118REV2/* Test Mode 7: This test mode tests the operation ofthe LEDS’s by turning all of them on and off. */case 0x07: toggle_all_leds();b

Strany 20

AN118AN118REV2 27/**************************************************************//* Routine - Delay

Strany 21

AN11828 AN118REV2;****************************************************************;* Routine - transfer_byte;* Input - Byte to be transmitte

Strany 22

AN118AN118REV2 29;****************************************************************;* Routine - RXSER;* Input - none;* Output - Byte rec

Strany 23

AN118AN118REV2 3final byte with its LSB at logic 0 are needed to resetthe serial port). This places the ADC in the com-mand state, where it awaits a v

Strany 24

AN11830 AN118REV2;****************************************************************;* Routine - TXSER;* Input - Byte to be transmitted is pla

Strany 25

• Notes •

Strany 27

AN1184 AN118REV2Figure 4. Write-Cycle TimingFigure 5. Read-Cycle TimingCommand Time8SCLKs8SCLKs Clear SDO FlagData SDO Continuous Conversion ReadSDO

Strany 28

AN118AN118REV2 53.5 Decoding PC CommandsThe decode_command routine is where most of thefunctionality of the program lies. It consists ofmany smaller

Strany 29

AN1186 AN118REV2data is then transferred to the ADC, and SDO ispolled until the conversion is ready. A byte of zerosis then transmitted to the ADC to

Strany 30

AN118AN118REV2 7tines, the user must place the DIP switches backinto the ‘000’ position and reset the evaluationboard. Each of the seven test modes is

Strany 31 - • Notes •

AN1188 AN118REV2board, and is entered by setting the DIPs to ‘111’.Immediately upon entering mode 7, thetoggle_all_leds routine is called to blink the

Strany 32

AN118AN118REV2 97. APPENDIX: 80C51 MICROCONTROLLER CODE/*CS5521/22/23/24/28 Runtime Constants and Prototypes*//*PROTOTYPES*/void initialize(void);

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