Cirrus-logic CDB53L30 Uživatelský manuál stáhnout pdf (Strana 20)

20 DS963DB1

CDB53L30

5 Performance Plots

Figure 5-17. THD+N (Relative) vs. Frequency,

Preamp Setting: 0 dB, –1 dBFS

Figure 5-18. THD+N (Relative) vs. Frequency,

Preamp Setting: +10 dB, –1 dBFS

Figure 5-19. THD+N (Relative) vs. Frequency,

Preamp Setting: +20 dB, –1 dBFS

Figure 5-20. THD+N (Relative) vs. Level, Preamp Setting: 0 dB,

PGA Setting: 0 dB, 1 kHz

Figure 5-21. THD+N (Relative) vs. Level, Preamp Setting: 0 dB,

PGA Setting: +12 dB, 1 kHz

Figure 5-22. THD+N (Relative) vs. Level,

Preamp Setting: +10 dB, PGA Setting: 0 dB, 1 kHz















 N    N N N N

PGA Setting: +12 dB

PGA Setting: 0 dB

Note: The low-frequency distortion

is dominated by the MLCC Class II

DC blocking capacitor (0.1 F). To

reduce this distortion, reduce the

corner frequency by selecting a

larger cap, or choose a different cap

type such as film or MLCC Class I.















 N    N N N N

PGA Setting: 0 dB

PGA Setting: +12 dB















 N    N N N N

PGA Setting: +12 dB

PGA Setting: 0 dB





















     

G%U





















     

G%U





















     

G%U

1 2 ... 15 16 17 18 19 20 21 22 23 24 25 ... 36 37

Komentáře k této Příručce

Žádné komentáře

Cirrus-logic CDB53L30 Uživatelský manuál Strana 20

Komentáře k této Příručce

Související produkty a manuály pro Hardware Cirrus-logic CDB53L30