Cirrus-logic CS4970x4 Uživatelský manuál

Copyright 2013 Cirrus Logic, Inc. MAR 2013DS810UM6http://www.cirrus.comCS4953x4/CS4970x4 32-bit Audio DSP FamilyPreliminary Product InformationThis do

x Copyright 2013 Cirrus Logic, Inc. DS810UM6CS4953x4/CS4970x4 System Designer’s Guide Figure 8-19. Displaying CDM Window ...

CS4953x4/CS4970x4 DSP Manager API DescriptionCS4953x4/CS4970x4 System Designer’s GuideDS810UM6 Copyright 2013 Cirrus Logic, Inc 7-7AND Command = 0xE

7-8 Copyright 2013 Cirrus Logic, Inc. DS810UM6CS4953x4/CS4970x4 DSP Manager API DescriptionCS4953x4/CS4970x4 System Designer’s Guide0x0005 DSP_CFG_OUT

CS4953x4/CS4970x4 DSP Manager API DescriptionCS4953x4/CS4970x4 System Designer’s GuideDS810UM6 Copyright 2013 Cirrus Logic, Inc 7-90x0009 DSP_CFG_VIRT

7-10 Copyright 2013 Cirrus Logic, Inc. DS810UM6CS4953x4/CS4970x4 DSP Manager API DescriptionCS4953x4/CS4970x4 System Designer’s GuideNote: For any qu

CS4953x4/CS4970x4 DSP Manager API DescriptionCS4953x4/CS4970x4 System Designer’s GuideDS810UM6 Copyright 2013 Cirrus Logic, Inc 7-11x= ppm mode define

7-12 Copyright 2013 Cirrus Logic, Inc. DS810UM6CS4953x4/CS4970x4 DSP Manager API DescriptionCS4953x4/CS4970x4 System Designer’s Guideucmd ef000007000m

Legacy API Still in UseCS4953x4/CS4970x4 System Designer’s GuideDS810UM6 Copyright 2013 Cirrus Logic, Inc 7-13 7.5 Legacy API Still in UseThere are ma

7-14 Copyright 2013 Cirrus Logic, Inc. DS810UM6Legacy API Still in UseCS4953x4/CS4970x4 System Designer’s GuideTable 7-6. Legacy Audio Manager Index V

Legacy API Still in UseCS4953x4/CS4970x4 System Designer’s GuideDS810UM6 Copyright 2013 Cirrus Logic, Inc 7-150x000C CHAN_LFE3_TRIM0x00000000 – 0x8000

7-16 Copyright 2013 Cirrus Logic, Inc. DS810UM6OS Firmware ModuleCS4953x4/CS4970x4 System Designer’s Guide 7.6 OS Firmware Module 7.6.1 OverviewThe ma

DS810UM6 Copyright 2013 Cirrus Logic, Inc. xiCS4953x4/CS4970x4 System Designer’s GuideTable 3-2. Bursty Data Input (BDI) Pins ...

7-17 Copyright 2013 Cirrus Logic, Inc. DS810UM6OS Firmware ModuleCS4953x4/CS4970x4 System Designer’s GuideA. Variable is valid in DSPA OS B. Variable

OverviewCS4953x4/CS4970x4 System Designer’s GuideDS810UM6 Copyright 2013 Cirrus Logic, Inc 8-1Chapter 8DSP Condenser 8.1 OverviewCirrus Logic provides

8-2 Copyright 2013 Cirrus Logic, Inc. DS810UM6Development FlowCS4953x4/CS4970x4 System Designer’s GuideIn addition to tools supporting this developmen

Development FlowCS4953x4/CS4970x4 System Designer’s GuideDS810UM6 Copyright 2013 Cirrus Logic, Inc 8-3for any given stream type, you can specify it no

8-4 Copyright 2013 Cirrus Logic, Inc. DS810UM6Elements of a ProjectCS4953x4/CS4970x4 System Designer’s Guide 8.3 Elements of a ProjectThe contents of

Elements of a ProjectCS4953x4/CS4970x4 System Designer’s GuideDS810UM6 Copyright 2013 Cirrus Logic, Inc 8-5COM mode — Selects the serial communication

8-6 Copyright 2013 Cirrus Logic, Inc. DS810UM6Elements of a ProjectCS4953x4/CS4970x4 System Designer’s Guide 8.3.3 Audio sources PageThe Audio sources

Elements of a ProjectCS4953x4/CS4970x4 System Designer’s GuideDS810UM6 Copyright 2013 Cirrus Logic, Inc 8-7 8.3.4 Sample rates PageThe Sample rates pa

8-8 Copyright 2013 Cirrus Logic, Inc. DS810UM6Elements of a ProjectCS4953x4/CS4970x4 System Designer’s Guide 8.3.5 Firmware components PageThe Firmwar

Elements of a ProjectCS4953x4/CS4970x4 System Designer’s GuideDS810UM6 Copyright 2013 Cirrus Logic, Inc 8-9Mode name — Customized name for selected sn

Introduction to CS4953x4/CS4970x4 System Designer’s GuideCS4953x4/CS4970x4 System Designer’s GuideDS810UM6 Copyright 2013 Cirrus Logic, Inc P-1 Prefac

8-10 Copyright 2013 Cirrus Logic, Inc. DS810UM6Elements of a ProjectCS4953x4/CS4970x4 System Designer’s Guide 8.3.7 Stream types PageThe Stream types

Elements of a ProjectCS4953x4/CS4970x4 System Designer’s GuideDS810UM6 Copyright 2013 Cirrus Logic, Inc 8-11 8.3.8 Power-up state PageThe Power-up sta

8-12 Copyright 2013 Cirrus Logic, Inc. DS810UM6Elements of a ProjectCS4953x4/CS4970x4 System Designer’s Guide 8.3.9 WAV update PageFor easy deployment

8-13 Copyright 2013 Cirrus Logic, Inc. DS810UM6Creating a Condenser Project using a ModelCS4953x4/CS4970x4 System Designer’s Guide 8.4 Creating a Cond

Creating a Condenser Project using a ModelCS4953x4/CS4970x4 System Designer’s GuideDS810UM6 Copyright 2013 Cirrus Logic, Inc 8-14Click OK and the mai

8-15 Copyright 2013 Cirrus Logic, Inc. DS810UM6Creating a Flash ImageCS4953x4/CS4970x4 System Designer’s GuideClick on Build->Create Flash ImageTh

Creating a Flash ImageCS4953x4/CS4970x4 System Designer’s GuideDS810UM6 Copyright 2013 Cirrus Logic, Inc 8-16 8.5.2 What Does the Image Contain?When t

8-17 Copyright 2013 Cirrus Logic, Inc. DS810UM6Using DSP CondenserCS4953x4/CS4970x4 System Designer’s Guide 8.6 Using DSP Condenser 8.6.1 How to use D

Using DSP CondenserCS4953x4/CS4970x4 System Designer’s GuideDS810UM6 Copyright 2013 Cirrus Logic, Inc 8-18 Figure 8-12. DSP Composer Sample Project, “

8-19 Copyright 2013 Cirrus Logic, Inc. DS810UM6Using DSP CondenserCS4953x4/CS4970x4 System Designer’s GuideCirrus Logic recommends that each project b

P-2 Copyright 2013 Cirrus Logic, Inc. DS810UM6Overview of the CS4953x4/CS4970x4 DSPCS4953x4/CS4970x4 System Designer’s Guide P.2.1 Chip FeaturesThe CS

Creating a Flash ImageCS4953x4/CS4970x4 System Designer’s GuideDS810UM6 Copyright 2013 Cirrus Logic, Inc 8-20 Figure 8-14. Sample Deliverables Directo

8-21 Copyright 2013 Cirrus Logic, Inc. DS810UM6Creating a Flash ImageCS4953x4/CS4970x4 System Designer’s Guide Figure 8-15. Blank SPI Flash Format 8.7

Creating a Flash ImageCS4953x4/CS4970x4 System Designer’s GuideDS810UM6 Copyright 2013 Cirrus Logic, Inc 8-22Note: This area of Flash may be destroyed

8-23 Copyright 2013 Cirrus Logic, Inc. DS810UM6Creating a Flash ImageCS4953x4/CS4970x4 System Designer’s Guide 8.7.2.1 Using the DSP Condenser Wizard

Creating a Flash ImageCS4953x4/CS4970x4 System Designer’s GuideDS810UM6 Copyright 2013 Cirrus Logic, Inc 8-246. At this point, the user can choose to

8-25 Copyright 2013 Cirrus Logic, Inc. DS810UM6Creating a Flash ImageCS4953x4/CS4970x4 System Designer’s Guide13.To program the serial Flash connected

Creating a Flash ImageCS4953x4/CS4970x4 System Designer’s GuideDS810UM6 Copyright 2013 Cirrus Logic, Inc 8-263. On the right, select CS497004_audio_ma

8-27 Copyright 2013 Cirrus Logic, Inc. DS810UM6DSP Response after Master Boot.CS4953x4/CS4970x4 System Designer’s Guide# DSP Flash status messagesword

Host ActivityCS4953x4/CS4970x4 System Designer’s GuideDS810UM6 Copyright 2013 Cirrus Logic, Inc 8-28'81' correspond to the autodetection mes

8-29 Copyright 2013 Cirrus Logic, Inc. DS810UM6Host ActivityCS4953x4/CS4970x4 System Designer’s Guide Figure 8-21. Changing Concurrency ModesNote: To

Overview of the CS4953x4/CS4970x4 DSPCS4953x4/CS4970x4 System Designer’s GuideDS810UM6 Copyright 2013 Cirrus Logic, Inc P-3 Figure P-2. CS4953x4 Chip

DSP Condenser Runtime ApplicationCS4953x4/CS4970x4 System Designer’s GuideDS810UM6 Copyright 2013 Cirrus Logic, Inc 9-1Chapter 9Using Runtime Condense

9-2 Copyright 2013 Cirrus Logic, Inc. DS810UM6DSP Condenser Runtime ApplicationCS4953x4/CS4970x4 System Designer’s Guide Figure 9-3. Program Flash on

Runtime GUI Current ProjectCS4953x4/CS4970x4 System Designer’s GuideDS810UM6 Copyright 2013 Cirrus Logic, Inc 9-37. Select the Board Input Source item

9-4 Copyright 2013 Cirrus Logic, Inc. DS810UM6Runtime GUI Current ProjectCS4953x4/CS4970x4 System Designer’s Guide 9.2.1.1 Connection to Board ButtonT

9-5 Copyright 2013 Cirrus Logic, Inc. DS810UM6Runtime GUI Current ProjectCS4953x4/CS4970x4 System Designer’s Guide 9.2.2.4.2 Configuration File Commma

Runtime GUI Current ProjectCS4953x4/CS4970x4 System Designer’s GuideDS810UM6 Copyright 2013 Cirrus Logic, Inc 9-6- brd_cfg -w board 00 02 24 02• DSP w

9-7 Copyright 2013 Cirrus Logic, Inc. DS810UM6Runtime GUI Current ProjectCS4953x4/CS4970x4 System Designer’s Guide 9.2.6 Source Status GroupThis group

Runtime GUI Current ProjectCS4953x4/CS4970x4 System Designer’s GuideDS810UM6 Copyright 2013 Cirrus Logic, Inc 9-8“Compressed”, “Uncompressed”, and “Un

9-9 Copyright 2013 Cirrus Logic, Inc. DS810UM6Runtime GUI Current ProjectCS4953x4/CS4970x4 System Designer’s Guide Figure 9-13. DSP Manager API Group

Runtime GUI Current ProjectCS4953x4/CS4970x4 System Designer’s GuideDS810UM6 Copyright 2013 Cirrus Logic, Inc 9-10 9.2.7.7 PPMThe PPM reflects the val

P-4 Copyright 2013 Cirrus Logic, Inc. DS810UM6CS4953x4/CS4970x4 Chip Functional OverviewCS4953x4/CS4970x4 System Designer’s Guide P.3 CS4953x4/CS4970x

IntroductionCS4953x4/CS4970x4 System Designer’s GuideDS810UM6 Copyright 2013 Cirrus Logic, Inc A-1Appendix AFAQ A.1 IntroductionAppendix A contains de

A-2 Copyright 2013 Cirrus Logic, Inc. DS810UM6List of Questions and AnswersCS4953x4/CS4970x4 System Designer’s GuideQ 2.How do I create deliverables u

A-3 Copyright 2013 Cirrus Logic, Inc. DS810UM6List of Questions and AnswersCS4953x4/CS4970x4 System Designer’s Guide5. Click on ‘Generate Deliverables

IntroductionCS4953x4/CS4970x4 System Designer’s GuideDS810UM6 Copyright 2013 Cirrus Logic, Inc B-1Appendix BOptional Features B.1 IntroductionAppendix

IntroductionCS4953x4/CS4970x4 System Designer’s GuideDS810UM6 Copyright 2013 Cirrus Logic, Inc C-1Appendix CLoading/Unloading Firmware Modules C.1 Int

C-2 Copyright 2013 Cirrus Logic, Inc. DS810UM6IntroductionCS4953x4/CS4970x4 System Designer’s Guide C.1.2.1 Loading DTS-ES Decoder in Matrix ModeThe h

IntroductionCS4953x4/CS4970x4 System Designer’s GuideDS810UM6 Copyright 2013 Cirrus Logic, Inc C-3UCMD Ef00000000000001x= SGEN mode, yy= SGEN uld id C

C-4 Copyright 2013 Cirrus Logic, Inc. DS810UM6IntroductionCS4953x4/CS4970x4 System Designer’s GuideNote: When the downmix option is chosen (also refle

IntroductionCS4953x4/CS4970x4 System Designer’s GuideDS810UM6 Copyright 2013 Cirrus Logic, Inc C-5 C.1.8 Dolby Virtual Speaker® 2See the Cirrus Logic

C-6 Copyright 2013 Cirrus Logic, Inc. DS810UM6IntroductionCS4953x4/CS4970x4 System Designer’s Guide C.1.9.2 Loading Dolby Headphone 2 with Dolby ProLo

CS4953x4/CS4970x4 Chip Functional OverviewCS4953x4/CS4970x4 System Designer’s GuideDS810UM6 Copyright 2013 Cirrus Logic, Inc P-5for compressed data in

IntroductionCS4953x4/CS4970x4 System Designer’s GuideDS810UM6 Copyright 2013 Cirrus Logic, Inc C-7 C.1.11 DTS-HD™ Master AudioSee the Cirrus Logic app

C-8 Copyright 2013 Cirrus Logic, Inc. DS810UM6IntroductionCS4953x4/CS4970x4 System Designer’s GuideCirrus Logic recommends that apply_crossbar_b be us

C-9 Copyright 2013 Cirrus Logic, Inc. DS810UM6Revision HistoryCS4953x4/CS4970x4 System Designer’s GuideWhen writing to the serial flash, the first loc

P-6 Copyright 2013 Cirrus Logic, Inc. DS810UM6Firmware OverviewCS4953x4/CS4970x4 System Designer’s Guide P.3.11 DMA ControllerThe DMA controller conta

CS40700x Pin DescriptionsCS4953x4/CS4970x4 System Designer’s GuideDS810UM6 Copyright 2013 Cirrus Logic, Inc P-7 P.4.2 DSP CondenserCirrus Logic provid

P-8 Copyright 2013 Cirrus Logic, Inc. DS810UM6CS40700x Pin DescriptionsCS4953x4/CS4970x4 System Designer’s Guide P.5.1.2 GroundFor two-layer circuit b

ii Copyright 2013 Cirrus Logic, Inc. DS810UM6CS4953x4/CS4970x4 System Designer’s GuideContacting Cirrus Logic Support For all product questions and in

CS40700x Pin DescriptionsCS4953x4/CS4970x4 System Designer’s GuideDS810UM6 Copyright 2013 Cirrus Logic, Inc P-9 P.5.2.2 PLLThe internal phase locked l

P-10 Copyright 2013 Cirrus Logic, Inc. DS810UM6CS40700x Pin DescriptionsCS4953x4/CS4970x4 System Designer’s Guide Figure P-4. Crystal Oscillator Circu

CS4970x4 Pin AssignmentsCS4953x4/CS4970x4 System Designer’s GuideDS810UM6 Copyright 2013 Cirrus Logic, Inc P-11Configuration and control of the CS4953

DS810UM6 Copyright 2013 Cirrus Logic P-12CS4970x4 Pin AssignmentsCS4953x4/CS4970x4 System Designer’s GuideTable P-10. CS4970x4 Pin Assignments for 14

DS810UM6 Copyright 2013 Cirrus Logic P-13CS4970x4 Pin AssignmentsCS4953x4/CS4970x4 System Designer’s Guide25 - GPIO25 General Purpose Input/Output1. U

DS810UM6 Copyright 2013 Cirrus Logic P-14CS4970x4 Pin AssignmentsCS4953x4/CS4970x4 System Designer’s Guide60 89 VDDIO4 I/O power supply voltage 3.3V P

DS810UM6 Copyright 2013 Cirrus Logic P-15CS4970x4 Pin AssignmentsCS4953x4/CS4970x4 System Designer’s Guide93 121RESETChip Reset 3.3V (5V tol) In94 122

DS810UM6 Copyright 2013 Cirrus Logic P-16CS4970x4 Pin AssignmentsCS4953x4/CS4970x4 System Designer’s Guide106 - GPIO10 General Purpose Input/Output1.

DS810UM6 Copyright 2013 Cirrus Logic P-17CS4970x4 Pin AssignmentsCS4953x4/CS4970x4 System Designer’s Guide117 - GPIO3 General Purpose Input/Output1. P

DS810UM6 Copyright 2013 Cirrus Logic P-18CS4970x4 Pin AssignmentsCS4953x4/CS4970x4 System Designer’s Guide138 30 DAI1_LRCLKPCM Audio Input Sample Rate

DS810UM6 Copyright 2013 Cirrus Logic, Inc. iiiCS4953x4/CS4970x4 System Designer’s GuideContents Contents . . . . . . . . . . . . . . . . . . . . . . .

DS810UM6 Copyright 2013 Cirrus Logic P-19CS4953x4 Pin AssignmentsCS4953x4/CS4970x4 System Designer’s Guide P.7 CS4953x4 Pin AssignmentsTable P-11 show

DS810UM6 Copyright 2013 Cirrus Logic P-20CS4953x4 Pin AssignmentsCS4953x4/CS4970x4 System Designer’s Guide17 49 GPIO15General Purpose Input/Output1. D

DS810UM6 Copyright 2013 Cirrus Logic P-21CS4953x4 Pin AssignmentsCS4953x4/CS4970x4 System Designer’s Guide38 66 EXT_WE Flash Write Enable3.3V (5V tol)

DS810UM6 Copyright 2013 Cirrus Logic P-22CS4953x4 Pin AssignmentsCS4953x4/CS4970x4 System Designer’s Guide58 87 SD_A9 SDRAM Address Bit 9 EXT_A9 Flash

DS810UM6 Copyright 2013 Cirrus Logic P-23CS4953x4 Pin AssignmentsCS4953x4/CS4970x4 System Designer’s Guide79 108 SD_CASSDRAM Column Address Strobe3.3V

DS810UM6 Copyright 2013 Cirrus Logic P-24CS4953x4 Pin AssignmentsCS4953x4/CS4970x4 System Designer’s Guide99 126 GPIO35General Purpose Input/OutputSCP

DS810UM6 Copyright 2013 Cirrus Logic P-25CS4953x4 Pin AssignmentsCS4953x4/CS4970x4 System Designer’s Guide108 - GPIO41General Purpose Input/Output1. P

DS810UM6 Copyright 2013 Cirrus Logic P-26CS4953x4 Pin AssignmentsCS4953x4/CS4970x4 System Designer’s Guide-11GPIO2General Purpose Input/Output1. UART_

DS810UM6 Copyright 2013 Cirrus Logic P-27CS4953x4 Pin AssignmentsCS4953x4/CS4970x4 System Designer’s Guide§§1138 30 DAI1_LRCLKPCM Audio Input Sample R

OverviewCS4953x4/CS4970x4 System Designer’s GuideDS810UM6 Copyright 2013 Cirrus Logic, Inc 1-1Chapter 1Operational Modes 1.1 OverviewThe CS4953x4/CS49

iv Copyright 2013 Cirrus Logic, Inc. DS810UM6CS4953x4/CS4970x4 System Designer’s GuideChapter 2. Serial Communication Mode...

1-2 Copyright 2013 Cirrus Logic, Inc. DS810UM6Operational Mode SelectionCS4953x4/CS4970x4 System Designer’s Guidehttp://www.datasheet4u.com/html/A/T/4

DS810UM6 Copyright 2013 Cirrus Logic, Inc 1-3Booting the DSP in Master Boot ModeCS4953x4/CS4970x4 System Designer’s GuideTable 1-2. Supported SPI Flas

DS810UM6 Copyright 2013 Cirrus Logic, Inc 1-4Booting the DSP in Master Boot ModeCS4953x4/CS4970x4 System Designer’s Guide Figure 1-2. CS497004, LQFP 1

DS810UM6 Copyright 2013 Cirrus Logic, Inc 1-5Booting the DSP in Master Boot ModeCS4953x4/CS4970x4 System Designer’s Guide Figure 1-3. CS497004/CS4963x

1-6 Copyright 2013 Cirrus Logic, Inc. DS810UM6Booting the DSP in Master Boot ModeCS4953x4/CS4970x4 System Designer’s GuideThe typical connection diagr

Booting the DSP in Master Boot ModeCS4953x4/CS4970x4 System Designer’s GuideDS810UM6 Copyright 2013 Cirrus Logic, Inc 1-7 Figure 1-4. Master Boot Flow

Booting the DSP in Master Boot ModeCS4953x4/CS4970x4 System Designer’s GuideDS810UM6 Copyright 2013 Cirrus Logic, Inc 1-87. If the message is “Flash i

IntroductionCS4953x4/CS4970x4 System Designer’s GuideDS810UM6 Copyright 2013 Cirrus Logic, Inc 2-1Chapter 2Serial Communication Mode 2.1 IntroductionT

SPI PortCS4953x4/CS4970x4 System Designer’s GuideDS810UM6 Copyright 2013 Cirrus Logic, Inc 2-2device on the bus may respond to one or more unique comm

2-3 Copyright 2013 Cirrus Logic, Inc. DS810UM6SPI PortCS4953x4/CS4970x4 System Designer’s Guide 2.4.1 SPI System Bus DescriptionThe SPI bus is a multi

DS810UM6 Copyright 2013 Cirrus Logic, Inc. vCS4953x4/CS4970x4 System Designer’s GuideChapter 5. External Memory Interfaces...

SPI PortCS4953x4/CS4970x4 System Designer’s GuideDS810UM6 Copyright 2013 Cirrus Logic, Inc 2-4signal is low. The bus is free only when all Slave SCP1_

2-5 Copyright 2013 Cirrus Logic, Inc. DS810UM6SPI PortCS4953x4/CS4970x4 System Designer’s Guide Figure 2-3. SPI Write Flow Diagram 2.4.3.2 SPI Write P

SPI PortCS4953x4/CS4970x4 System Designer’s GuideDS810UM6 Copyright 2013 Cirrus Logic, Inc 2-6bytes of any message length, so long as the correct hard

2-7 Copyright 2013 Cirrus Logic, Inc. DS810UM6SPI PortCS4953x4/CS4970x4 System Designer’s Guide5. If SCP1_IRQ is still low after 4 bytes, then proceed

DS810UM6 Copyright 2013 Cirrus Logic, Inc 2-8SPI PortCS4953x4/CS4970x4 System Designer’s Guide Figure 2-5. Sample Waveform for SPI Write Functional Ti

I2C PortCS4953x4/CS4970x4 System Designer’s GuideDS810UM6 Copyright 2013 Cirrus Logic, Inc 2-9 2.4.3.5 SCP1_IRQ BehaviorThe SCP1_IRQ signal is not par

I2C PortCS4953x4/CS4970x4 System Designer’s GuideDS810UM6 Copyright 2013 Cirrus Logic, Inc 2-10 2.5.1 I2C System Bus DescriptionDevices can be conside

2-11 Copyright 2013 Cirrus Logic, Inc. DS810UM6I2C PortCS4953x4/CS4970x4 System Designer’s Guide 2.5.2 I2C Bus DynamicsThe Start condition for an I2C

I2C PortCS4953x4/CS4970x4 System Designer’s GuideDS810UM6 Copyright 2013 Cirrus Logic, Inc 2-12the CS4953x4/CS4970x4 is 1000000b (0x80). The R/W bit i

2-13 Copyright 2013 Cirrus Logic, Inc. DS810UM6I2C PortCS4953x4/CS4970x4 System Designer’s Guide Figure 2-11. Data Byte with ACK and NACKAfter an ACK

vi Copyright 2013 Cirrus Logic, Inc. DS810UM6CS4953x4/CS4970x4 System Designer’s Guide 8.3.2 Search paths Page...

I2C PortCS4953x4/CS4970x4 System Designer’s GuideDS810UM6 Copyright 2013 Cirrus Logic, Inc 2-14 Figure 2-13. Stop Condition with ACK and NACKIf a Slav

2-15 Copyright 2013 Cirrus Logic, Inc. DS810UM6I2C PortCS4953x4/CS4970x4 System Designer’s Guide 2.5.3.2 Performing a Serial I2C WriteInformation prov

I2C PortCS4953x4/CS4970x4 System Designer’s GuideDS810UM6 Copyright 2013 Cirrus Logic, Inc 2-16 2.5.3.3 I2C Write Protocol1. An I2C transfer is initia

2-17 Copyright 2013 Cirrus Logic, Inc. DS810UM6I2C PortCS4953x4/CS4970x4 System Designer’s Guide Figure 2-15. I2C Read Flow DiagramSCP1_IRQ (LOW)?BYTE

I2C PortCS4953x4/CS4970x4 System Designer’s GuideDS810UM6 Copyright 2013 Cirrus Logic, Inc 2-18 2.5.3.5 I2C Read Procedure1. An I2C read transaction i

DS810UM6 Copyright 2013 Cirrus Logic, Inc 2-19I2C PortCS4953x4/CS4970x4 System Designer’s Guide Figure 2-16. Sample Waveform for I2C Write Functional

2-20 Copyright 2013 Cirrus Logic, Inc. DS810UM6I2C PortCS4953x4/CS4970x4 System Designer’s Guide 2.5.3.6 SCP1_IRQ BehaviorOnce the BOOT_ASSIST_A (.ULD

IntroductionCS4953x4/CS4970x4 System Designer’s GuideDS810UM6 Copyright 2013 Cirrus Logic, Inc 3-1Chapter 3Audio Input Interfaces 3.1 IntroductionCS49

3-2 Copyright 2013 Cirrus Logic, Inc. DS810UM6Digital Audio Input Port DescriptionCS4953x4/CS4970x4 System Designer’s Guide 3.2.2 Supported DAI Functi

Digital Audio Input Port DescriptionCS4953x4/CS4970x4 System Designer’s GuideDS810UM6 Copyright 2013 Cirrus Logic, Inc 3-3 Figure 3-1. DAI Port Block

DS810UM6 Copyright 2013 Cirrus Logic, Inc. viiCS4953x4/CS4970x4 System Designer’s Guide 9.2.2.4 Command Field ...

3-4 Copyright 2013 Cirrus Logic, Inc. DS810UM6DAI Hardware ConfigurationCS4953x4/CS4970x4 System Designer’s Guidethe right subframe is presented when

DAI Hardware ConfigurationCS4953x4/CS4970x4 System Designer’s GuideDS810UM6 Copyright 2013 Cirrus Logic, Inc 3-5. Table 3-3. Input Data Format Configu

3-6 Copyright 2013 Cirrus Logic, Inc. DS810UM6DAI Hardware ConfigurationCS4953x4/CS4970x4 System Designer’s Guide..1 Data Clocked in on SCLK Falling E

Digital Audio Input Port DescriptionCS4953x4/CS4970x4 System Designer’s GuideDS810UM6 Copyright 2013 Cirrus Logic, Inc 3-7 3.4 Digital Audio Input Por

3-8 Copyright 2013 Cirrus Logic, Inc. DS810UM6Digital Audio Input Port DescriptionCS4953x4/CS4970x4 System Designer’s Guide Figure 3-3. DSD Port Block

IntroductionCS4953x4/CS4970x4 System Designer’s GuideDS810UM6 Copyright 2013 Cirrus Logic, Inc 4-1Chapter 4Audio Output Interface 4.1 IntroductionThe

4-2 Copyright 2013 Cirrus Logic, Inc. DS810UM6Digital Audio Output Port DescriptionCS4953x4/CS4970x4 System Designer’s GuideDAO1_SCLK is the bit clock

Digital Audio Output Port DescriptionCS4953x4/CS4970x4 System Designer’s GuideDS810UM6 Copyright 2013 Cirrus Logic, Inc 4-3 4.2.2 Supported DAO Functi

4-4 Copyright 2013 Cirrus Logic, Inc. DS810UM6Digital Audio Output Port DescriptionCS4953x4/CS4970x4 System Designer’s Guide 4.2.3.3 One-line Data Mod

Digital Audio Output Port DescriptionCS4953x4/CS4970x4 System Designer’s GuideDS810UM6 Copyright 2013 Cirrus Logic, Inc 4-5Table 4-2 shows values and

viii Copyright 2013 Cirrus Logic, Inc. DS810UM6CS4953x4/CS4970x4 System Designer’s Guide C.1.5 Dolby Digital®PLus...

4-6 Copyright 2013 Cirrus Logic, Inc. DS810UM6Digital Audio Output Port DescriptionCS4953x4/CS4970x4 System Designer’s Guide2DAO_MCLK = 256 FSDAO1_SCL

Digital Audio Output Port DescriptionCS4953x4/CS4970x4 System Designer’s GuideDS810UM6 Copyright 2013 Cirrus Logic, Inc 4-79DAO_MCLK = 384 FSDAO1_SCLK

4-8 Copyright 2013 Cirrus Logic, Inc. DS810UM6Digital Audio Output Port DescriptionCS4953x4/CS4970x4 System Designer’s GuideTable 4-5 shows values and

Digital Audio Output Port DescriptionCS4953x4/CS4970x4 System Designer’s GuideDS810UM6 Copyright 2013 Cirrus Logic, Inc 4-9Table 4-6 shows values and

4-10 Copyright 2013 Cirrus Logic, Inc. DS810UM6Digital Audio Output Port DescriptionCS4953x4/CS4970x4 System Designer’s GuideTo summarize the XMTA/XMI

4-11 Copyright 2013 Cirrus Logic, Inc. DS810UM6Digital Audio Output Port DescriptionCS4953x4/CS4970x4 System Designer’s Guide§§Table 4-11. DSP Bypass

SDRAM ControllerCS4953x4/CS4970x4 System Designer’s GuideDS810UM6 Copyright 2013 Cirrus Logic, Inc 5-1Chapter 5External Memory Interfaces 5.1 SDRAM Co

5-2 Copyright 2013 Cirrus Logic, Inc. DS810UM6SDRAM ControllerCS4953x4/CS4970x4 System Designer’s Guide 5.1.1 SDRAM Controller InterfaceThe physical i

SDRAM ControllerCS4953x4/CS4970x4 System Designer’s GuideDS810UM6 Copyright 2013 Cirrus Logic, Inc 5-3 5.1.3 Configuring SDRAM ParametersNot all SDRAM

5-4 Copyright 2013 Cirrus Logic, Inc. DS810UM6SDRAM ControllerCS4953x4/CS4970x4 System Designer’s GuideTable 5-2. SDRAM Interface ParametersMnemonic H

DS810UM6 Copyright 2013 Cirrus Logic, Inc. ixCS4953x4/CS4970x4 System Designer’s Guide Figure 2-7. Serial Control Port Internal Block Diagram ...

SDRAM ControllerCS4953x4/CS4970x4 System Designer’s GuideDS810UM6 Copyright 2013 Cirrus Logic, Inc 5-5DynamictAPRConfigure the last data out to active

5-6 Copyright 2013 Cirrus Logic, Inc. DS810UM6SPI Flash InterfaceCS4953x4/CS4970x4 System Designer’s Guide 5.2 SPI Flash InterfaceThe CS4953x4/CS4970x

IntroductionCS4953x4/CS4970x4 System Designer’s GuideDS810UM6 Copyright 2013 Cirrus Logic, Inc 6-1Chapter 6System Design Requirements for SPDIF andHDM

IntroductionCS4953x4/CS4970x4 System Designer’s GuideDS810UM6 Copyright 2013 Cirrus Logic, Inc 6-2 6.1.2.2 Decoding Stream Types Over HDMIWhen decodin

IntroductionCS4953x4/CS4970x4 System Designer’s GuideDS810UM6 Copyright 2013 Cirrus Logic, Inc 7-1Chapter 7Overview of Common Firmware Modules 7.1 Int

7-2 Copyright 2013 Cirrus Logic, Inc. DS810UM6Firmware MessagingCS4953x4/CS4970x4 System Designer’s GuideThe overlay architecture thus imposes limits

Firmware MessagingCS4953x4/CS4970x4 System Designer’s GuideDS810UM6 Copyright 2013 Cirrus Logic, Inc 7-3 7.3.3 Solicited ReadA solicited read can be t

7-4 Copyright 2013 Cirrus Logic, Inc. DS810UM6Firmware MessagingCS4953x4/CS4970x4 System Designer’s GuideThe 8-byte unsolicited read messages from the

Firmware MessagingCS4953x4/CS4970x4 System Designer’s GuideDS810UM6 Copyright 2013 Cirrus Logic, Inc 7-5 7.3.8 DSP_LAST_ACCN_MSGThe DSP_LAST_ACCN_MSG

7-6 Copyright 2013 Cirrus Logic, Inc. DS810UM6CS4953x4/CS4970x4 DSP Manager API DescriptionCS4953x4/CS4970x4 System Designer’s Guide 7.4 CS4953x4/CS49