Cirrus-logic CS4970x4 Uživatelský manuál stáhnout pdf (Strana 54)

SPI Port

CS4953x4/CS4970x4 System Designer’s Guide

Figure 2-5. Sample Waveform for SPI Write Functional Timing

Figure 2-6. Sample Waveform for SPI Read Functional Timing

Note:

1. IRQ remains low until the rising edge of the clock for the last bit of the last byte to be read from the SPI Slave.

2. After going high, IRQ remains high until the CS

signal is raised to end the SPI transaction. If there are more bytes to read, IRQ will fall after

has gone high.

SCP1_CLK

SCP1_MOSI

Data Byte 3 (MSB)7-bit Address

Data Byte 2 Data Byte 1 Data Byte 0 (LSB)

SCP1_CS

SCP1_CLK

SCP1_MOSI

Data Byte 3 (MSB)

7-bit Address

Data Byte 2 Data Byte 1 Data Byte 0 (LSB)

SCP1_CS

SCP1_MISO

SCP1_IRQ

1 2 ... 49 50 51 52 53 54 55 56 57 58 59 ... 161 162

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Cirrus-logic CS4970x4 Uživatelský manuál Strana 54