Cirrus-logic CS61583 Uživatelský manuál

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Features
Dual T1/E1 Line Interface
Low Power Consumption
(Typically 220mW per Line Interface)
Matched Impedance Transmit Drivers
Common Transmit and Receive Transform-
ers for all Modes
Selectable Jitter Attenuation for Transmit
or Receive Paths
Supports JTAG Boundary Scan
Hardware Mode Derivative of the CS61584
General Description
The CS61583 is a dual line interface for T1/E1 applica-
tions, designed for high-volume cards where low power
and high density are required. Each channel features
individual control and status pins which eliminates the
need for external microprocessor support. The
matched impedance drivers reduce power consumption
and provide substantial return loss to insure superior
T1/E1 pulse quality.
The CS61583 provides JTAG boundary scan to en-
hance system testability and reliability. The CS61583 is
a 5 volt device and is a hardware mode derivative of
the CS61584.
ORDERING INFORMATION
CS61583-IL5: 68-pin PLCC, -40 to +85 °C
CS61583-IQ5: 64-pin TQFP, -40 to +85 °C
JULY ’96
DS172PP5
1
Crystal Semiconductor Corporation
P. O. Box 17847, Austin, Texas, 78760
(512) 445 7222 FAX:(512) 445 7581
Dual T1/E1 Line Interface
TTIP1
TRING1
RRING1
RTIP1
DRIVER
CONTROL
TCLK1
RCLK1
JTAG
4
REFCLK 1XCLK
TV+ TGND RV+ RGND DV+ DGND AV+ AGND
BGREF
2 2 2 2 3 2
CLOCK GENERATOR
TPOS1/
TNEG1/
RPOS1/
RNEG1/
LOS1 LOS2
PULSE
SHAPING
CIRCUITRY
CLOCK &
DATA
RECOVERY
LOS
DETECT
TAOS
TTIP2
TRING2
RRING2
RTIP2
DRIVER
TCLK2
RCLK2
TPOS2/
TNEG2/
RPOS2/
RNEG2/
PULSE
SHAPING
CIRCUITRY
CLOCK &
DATA
RECOVERY
TAOS
LOS
DETECT
RESET
CLKE TAOS1
LLOOP1
RLOOP1
CON01
CON11
CON21
RLOOP2
LLOOP2
TAOS2
CON02
CON12
CON22
AMI2AMI1
CODER2CODER1ATTEN1
ATTEN2
JITTER
ATTENUATOR
E
N
C
O
D
E
R
D
E
C
O
D
E
R
L
O
C
A
L
L
O
O
P
B
A
C
K
R
E
M
O
T
E
L
O
O
P
B
A
C
K
JITTER
ATTENUATOR
E
N
C
O
D
E
R
D
E
C
O
D
E
R
L
O
C
A
L
L
O
O
P
B
A
C
K
R
E
M
O
T
E
L
O
O
P
B
A
C
K
TDATA1
AIS1
RDATA1
BPV1
TDATA2
AIS2
RDATA2
BPV2
RECEIVER
RECEIVER
CS61583
Copyright
Crystal Semiconductor Corporation 1996
(All Rights Reserved)
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Shrnutí obsahu

Strany 1 - CS61583

Features•Dual T1/E1 Line Interface•Low Power Consumption(Typically 220mW per Line Interface)•Matched Impedance Transmit Drivers•Common Transmit and Re

Strany 2 - 2 DS172PP5

tional benefit of the internal impedance matchingis a 50 percent reduction in power consumptioncompared to implementing return loss using ex-ternal re

Strany 3 - ABSOLUTE MAXIMUM RATINGS

during the transmission of both marks andspaces. This improves signal quality by minimiz-ing reflections from the transmitter. Impedancematching also

Strany 4 - ANALOG SPECIFICATIONS (T

ter will output a maximum of 50 mA-rms, as re-quired by European specification BS6450.RECEIVERThe receiver extracts data and clock from theT1/E1 signa

Strany 5

age incoming frequency (e.g. following a devicereset) the attenuator will tolerate a minimum of22 UIs before the overflow/underflow mecha-nism occurs.

Strany 6

Alarm Indication SignalIn coder mode, the TNEG pin becomes thealarm indication signal (AIS) output controlledby the receiver. The receiver detects the

Strany 7 - Any Digital Output

receive circuitry is calibrated if REFCLK andTCLK are present.JTAG BOUNDARY SCANBoard testing is supported through JTAG bound-ary scan. Using boundary

Strany 8

The first bit (shifted in first) selects between anoutput-enabled state (bit set to 1) or high-imped-ance state (bit set to 0). The second bit shifted

Strany 9 - DS172PP5 9

JTAG Instructions and Instruction Register (IR)The instruction register (2 bits) allows the in-struction to be shifted into the JTAG circuit. Theinstr

Strany 10 - 10 DS172PP5

instruction register and all test data registers re-tain their previous state. When J-TMS is highand a rising edge is applied to J-TCK, the con-troll

Strany 11

The test data register selected by the current in-struction retains its previous value during thisstate. The instruction does not change in thisstate

Strany 12

Table of ContentsBlock Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1SpecificationsAbsolute Maximum Ratin

Strany 13

The test data register selected by the current in-struction retains its previous value during thisstate. The instruction does not change in thisstate

Strany 14 - 14 DS172PP5

TCKTMSController stateTDIIR shift-registerParallel output of IRParallel Input to TDRTDR shift-registerParallel output of TDRRegister selectedTDO enabl

Strany 15 - DS172PP5 15

TCKTMSController stateTDIParallel Input to IRIR shift-registerParallel output of IRParallel Input to TDRTDR shift-registerRegister SelectedTDO enableT

Strany 16

PIN DESCRIPTIONS111315171921232513579 676563613533312927 37 39 41 434547495153555759CS6158368-Pin PLCCTop ViewDGND1CON01TAOS2TAOS1LLOOP2LLOOP1RLOOP1AT

Strany 17

CS6158364-Pin TQFPTop View464442403836483418 20 22 24 26 28 30 3264 62 60 58 56 54 52 501468101214216DV+DGND3CON02CON11CON12CON21CON22AMI1RCLK2RPOS2/R

Strany 18 - 18 DS172PP5

Power SuppliesAGND1, AGND2 : Analog Ground (PLCC pins 31, 33; TQFP pins 21, 23)Analog supply ground pins.AV+ : Analog Power Supply (PLCC pin 34; TQ

Strany 19 - DS172PP5 19

TCLK1, TCLK2 : Transmit Clock (PLCC pins 13, 56; TQFP pins 4, 45)TPOS1, TPOS2 : Transmit Positive Data (PLCC pins 14, 55; TQFP pins 5, 44)TNEG1, TNEG

Strany 20 - 20 DS172PP5

CODER1, CODER2 : Coder Mode Configuration (PLCC pins 24, 45; TQFP pins 15, 34)Setting CODER high causes the Coder Mode to be enabled. In Coder Mode,

Strany 21 - DS172PP5 21

LOS1, LOS2 : Loss of Signal (PLCC pins 16, 53; TQFP pins 7, 42)The LOS indication goes high when 175 ± 15 consecutive zeros are received on the linei

Strany 22 - 22 DS172PP5

PHYSICAL DIMENSIONS68 pinPLCCEEDD11xezuAA1yBEMAXMIN MAXMINMILLIMETERS INCHESDIMA5.084.20 .200.165DD124.79 25.30 .976 .996B0.530.38 .021.015eA2.29 .090

Strany 23 - PIN DESCRIPTIONS

ABSOLUTE MAXIMUM RATINGSParameter Symbol Min Max UnitsDC Supply (TV+1, TV+2, RV+1, RV+2, AV+, DV+) (Note 1) - 6.0 VInput Voltage (Any Pin) VinRGND - 0

Strany 24

MILLIMETERS INCHES641DIMDDeBAALC0.4610.3940.400.01610.0011.700.14-0.00MIN0.350.0771.66-MAX0.260.700.1770.006-0.00MIN0.0140.0030.068-MAX0.0100.0280.007

Strany 25 - DS172PP5 25

APPLICATIONSLine InterfaceFigure A1 illustrates a typical connection diagramand Table A1 lists the external components thatare required in T1 and E1 a

Strany 26 - 26 DS172PP5

resistor must be connected from BGREF toground to provide an internal current reference.De-coupling and filtering of the power supplies iscrucial for

Strany 27 - DS172PP5 27

Schematic & Layout Review ServiceConfirm OptimumSchematic & LayoutBefore Building Your Board.For Our Free Review ServiceCall Applications Engi

Strany 28 - 28 DS172PP5

Features••Socketed CS61583 Dual Line Interface••All Required Components for CS61583Evaluation••Locations to Evaluate Protection Circuitry••LED Status

Strany 29 - PHYSICAL DIMENSIONS

POWER SUPPLYAs shown on the evaluation board schematic inFigures 1-5, power is supplied to the board froman external +5 Volt supply connected to the t

Strany 30 - 30 DS172PP5

reset can be used to initialize the control logic.Both channels are powered up after exiting reset.TRANSMIT CIRCUITThe transmit clock and data signals

Strany 31

Crystal OscillatorA crystal oscillator may be inserted at socket U4in the orientation indicated by the silkscreen.Header J14 must be jumpered in the &

Strany 32

4. Closing a DIP switch on SW2, SW3, andSW4 towards the label sets the CS61583 controlpin of the same name to logic 1.5. When performing a manual loop

Strany 33 - Call: (512) 445-7222

RCLK1RPOS1RNEG1TCLK1TPOS1TNEG1LOS1J-TDODGND2J-TDITTIP1TV+1TGND1TRING1CODER1ATTEN0RTIP1RRING1101112131415RCLK1RPOS1RNEG1TCLK1TPOSTNEG357468171513161412

Strany 34 - CDB61583

DIGITAL CHARACTERISTICS (TA = -40 to 85 °C; power supply pins within ±5% of nominal)Parameter Symbol Min Typ Max UnitsHigh-Level Input Voltage (Note 7

Strany 35

RCLK2RPOS2RNEG2TCLK2TPOS2TNEG2LOS2AMI2J-TCKJ-TMSTTIP2TV+2TGND2TRING2CODER2CLKERTIP2RRING2U7CS61583CHANNEL 2595857565554RCLK2RPOS2RNEG2TCLK2TPOS2TNEG29

Strany 36

2468101214161820222426ATTEN1RLOOP1LLOOP1LLOOP2TAOS1TAOS2CON01DGND1DV+DGND3CON02CON11CON12CON21CON22AMI1U7CS61584CONTROL CIRCUITRY1 24 TAOS22 23 TAOS13

Strany 37

RV+1RGND1AGND1BGREFAGND2AV+RESETREFCLKRLOOP21XCLKRGND2RV+2U7CS61583TIMING CIRCUITRY2940C5.1µFVD+R2347KR104.99kC6C7.1µF1.0µFVD+VD+VD+SW112R1110KY11XCLK

Strany 38

VA+VD+J22J23V+GNDC16L1VD+Prototyping AreaZ147µFFigure 5. Common CircuitryCDB61583DB172PP1 43

Strany 39

Smart AnalogTM is a Trademark of Crystal Semiconductor Corporation

Strany 40

ANALOG SPECIFICATIONS (TA = -40 to 85 °C; power supply pins within ±5% of nominal)Parameter Min Typ Max UnitsTransmitterAMI Output Pulse Amplitudes (N

Strany 41 - Figure 3. Control Circuitry

SWITCHING CHARACTERISTICS - T1 CLOCK/DATA (TA = -40 to 85 °C; power supplypins within ±5% of nominal; Inputs: Logic 0 = 0V, Logic 1 = DV+) (See Figur

Strany 42 - Figure 4. Timing Circuitry

Any Digital Outputtrtf10% 10%90% 90%Figure 1. Signal Rise and Fall CharacteristicsRCLK(CLKE = 1)tpwl1tpwh1RCLK(CLKE =0)RPOSRNEGRDATABPVh1tsu1ttpw1

Strany 43

J-TCKJ-TMSJ-TDIJ-TDOtcyctdvtsuthFigure 4. JAG Switching CharacteristicsSWITCHING CHARACTERISTICS - JTAG (TA = - 40 ° to 85 ° C; TV+, RV+ = nominal

Strany 44

OVERVIEWThe CS61583 is a dual line interface for T1/E1applications, designed for high-volume cardswhere low power and high density are required.One bo

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