Cirrus-logic CS470xx Uživatelský manuál stáhnout pdf (Strana 8)

DS787PP9 8

4 Hardware Functional Description

Figure 4-2. CS47028 Top-level Block Diagram

Figure 4-3. CS47024 Top-level Block Diagram

x8

x4

x2

x2

DAC0

text

32-bit Core

in the CS47028 DSP

DMA

SPI / I

2

C

Control

I

2

S

I

2

S

I

2

S / S/PDIF

PLL

ROM

S

R

C

2

Peripheral Bus

Clock

Manager

Timers

RAM

X

GPIO

DAC1

DAC2

DAC3

DAC4

DAC5

DAC6

DAC7

MUX

S

R

C

1

ROM

RAM

ROM

RAM

P

Y

32K x 32-bit SRAM with three 2K blocks

Assignable to Program or Y Data memory

Memory Bus

I

2

S /

S/PDIF

Stereo Inputs

On Analog in

ADC2/3

DBC

(I

2

C Slave)

PIC

ADC’s & DAC’s operate

in Single ended or

Differential mode

S

R

C

3

8ch

8ch

SRC3 has 8

independent Channels

for In or Out

4ch

x8

x4

x2

x2

text

32-bit Core

in the CS47024 DSP

DMA

SPI / I

2

C

Control

I

2

S

I

2

S

I

2

S / S/PDIF

PLL

ROM

S

R

C

2

Peripheral Bus

Clock

Manager

Timers

RAM

X

GPIO

DAC0

DAC1

DAC2

DAC3

MUX

S

R

C

1

ROM

RAM

ROM

RAM

P

Y

32K x 32-bit SRAM with three 2K blocks

Assignable to Program or Y Data memory

Memory Bus

I

2

S /

S/PDIF

Stereo Inputs

On Analog in

ADC2/3

DBC

(I

2

C Slave)

PIC

ADC’s & DAC’s operate

in Single ended or

Differential mode

S

R

C

3

8ch

8ch

SRC3 has 8

independent Channels

for In or Out

4ch

1 2 3 4 5 6 7 8 9 10 11 12 13 ... 31 32

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