Cirrus-logic CS42L52 Uživatelský manuál

Copyright  Cirrus Logic, Inc. 2013 (All Rights Reserved)http://www.cirrus.comMAR ’13DS680F2Low-Power, Stereo CODEC with Headphone and Speaker AmpsSte

10 DS680F2CS42L523/1/131.1 I/O Pin CharacteristicsInput and output levels and associated power supply voltage are shown in the table below. Logic leve

DS680F2 11CS42L523/1/132. TYPICAL CONNECTION DIAGRAMNote 4Note 3Note 2Note 11 µF+1.8 V to +2.5 V0.1 µF1 µFDGNDVL0.1 µF+1.8 V to +3.3 VSCLSDARESET2 k

12 DS680F2CS42L523/1/133. CHARACTERISTIC AND SPECIFICATIONSRECOMMENDED OPERATING CONDITIONSAGND=DGND=0 V, All voltages with respect to ground.ABSOLUTE

DS680F2 13CS42L523/1/13ANALOG INPUT CHARACTERISTICS Test Conditions (unless otherwise specified): Input sine wave (relative to digital full scale): 1

14 DS680F2CS42L523/1/13ADC DIGITAL FILTER CHARACTERISTICS 5. Response is clock-dependent and will scale with Fs. Note that the response plots (Figur

DS680F2 15CS42L523/1/13ANALOG OUTPUT CHARACTERISTICS Test conditions (unless otherwise specified): Input test signal is a full-scale 997 Hz sine wave;

16 DS680F2CS42L523/1/138. See Figure 2. RL and CL reflect the recommended minimum resistance and maximum capacitance re-quired for the internal op-amp

DS680F2 17CS42L523/1/13PWM OUTPUT CHARACTERISTICS Test conditions (unless otherwise specified): Input test signal is a full scale 997 Hz signal; MCLK

18 DS680F2CS42L523/1/139. The PWM driver should be used in captive speaker systems only.10. Optimal PWM performance is achieved when MCLK > 12 MHz.

DS680F2 19CS42L523/1/13LINE OUTPUT VOLTAGE LEVEL CHARACTERISTICS Test conditions (unless otherwise specified): Input test signal is a full-scale 997 H

2 DS680F2CS42L523/1/13System Features 12, 24, and 27 MHz Master Clock Support in Addition to Typical Audio Clock Rates High-performance 24-bit Conve

20 DS680F2CS42L523/1/13SWITCHING SPECIFICATIONS - SERIAL PORTInputs: Logic 0 = DGND, Logic 1 = VL, SDOUT CLOAD = 15 pF. 14. After powering up the CS42

DS680F2 21CS42L523/1/13SWITCHING SPECIFICATIONS - I²C CONTROL PORTInputs: Logic 0 = DGND, Logic 1 = VL, SDA CL=30pF.16. Data must be held for sufficie

22 DS680F2CS42L523/1/13DC ELECTRICAL CHARACTERISTICS AGND = 0 V; All voltages with respect to ground. 17. Valid with the recommended capacitor values

DS680F2 23CS42L523/1/13POWER CONSUMPTION See (Note 20). 20. Unless otherwise noted, test conditions are as follows: All zeros input, slave mode, sampl

24 DS680F2CS42L523/1/134. APPLICATIONS4.1 Overview4.1.1 Basic ArchitectureThe CS42L52 is a highly integrated, low-power, 24-bit audio CODEC comprised

DS680F2 25CS42L523/1/134.2 Analog Inputs Referenced Control Register LocationAnalog Front EndPDN_PGAx ...PGAxVOL[5:0]...

26 DS680F2CS42L523/1/134.2.1 MIC InputsThe input pins 21, 22, 23, and 24 accept stereo line-level or microphone signals. For microphone inputs,either

DS680F2 27CS42L523/1/13 4.2.3 Noise GateThe noise gate may be used to mute signal levels that fall below a programmable threshold. This preventsthe A

28 DS680F2CS42L523/1/134.3 Analog Outputs Referenced Control Register LocationDSPDEEMPH...PMIXxMUTE...P

DS680F2 29CS42L523/1/134.3.1 Beep GeneratorThe Beep Generator generates audio frequencies across approximately two octave major scales. It offersthree

DS680F2 3CS42L523/1/13TABLE OF CONTENTS1. PIN DESCRIPTIONS ...

30 DS680F2CS42L523/1/13 4.3.2 LimiterWhen enabled, the limiter monitors the digital input signal before the DAC and PWM modulators, detectswhen levels

DS680F2 31CS42L523/1/134.4 Analog In to Analog Out PassthroughThe CS42L52 accommodates analog routing of the analog input signal directly to the headp

32 DS680F2CS42L523/1/134.4.2 Overriding the PGA Power DownTo accommodate automatic activation of the headphone amplifier when the SPK/HP_SW switch pin

DS680F2 33CS42L523/1/134.5.2 VP Battery CompensationThe CS42L52 provides the option to maintain a desired power output level, independent of the VP su

34 DS680F2CS42L523/1/13input master clock (MCLK) in Master Mode. Refer to the tables below for the required setting in register 05hand 06h associated

DS680F2 35CS42L523/1/134.7 Digital Interface Formats The serial port operates in standard I²S, Left-justified, Right-justified (DAC only), or DSP Mode

36 DS680F2CS42L523/1/13When configuring the 16-bit SDOUT word length with an 8 kHz sample rate in master mode and whenSCLK is set equal to MCLK, perfo

DS680F2 37CS42L523/1/134.9 Recommended Power-up Sequence1. Hold RESET low until the power supplies are stable. 2. Bring RESET high. 3. The default sta

38 DS680F2CS42L523/1/131. Write 0x99 to register 0x00. 2. Write 0xBA to register 0x3E. 3. Write 0x80 to register 0x47. 4. Write 1 to bit 7 in register

DS680F2 39CS42L523/1/13Since the read operation cannot set the MAP, an aborted write operation is used as a preamble. As shownin Figure 21, the write

4 DS680F2CS42L523/1/134.12.2.1 Map Increment (INCR) ... 395.

40 DS680F2CS42L523/1/135. REGISTER QUICK REFERENCEDefault values are shown below the bit names. Unless otherwise specified, all “Reserved” bits must m

DS680F2 41CS42L523/1/131Bh PCMMIXB Vol PMIXBMUTE PMIXBVOL6 PMIXBVOL5 PMIXBVOL4 PMIXBVOL3 PMIXBVOL2 PMIXBVOL1 PMIXBVOL0p58 00 0 0 000 01Ch BEEP Freq, O

42 DS680F2CS42L523/1/136. REGISTER DESCRIPTIONAll registers are read/write except for the Chip I.D. and Revision Register and Interrupt Status Registe

DS680F2 43CS42L523/1/13input path. The PGAxSEL bits may be used to isolate the input signal(s) from the PGA outputs. When the PGA is powered down, no

44 DS680F2CS42L523/1/136.4 Power Control 3 (Address 04h)6.4.1 Headphone Power ControlConfigures how the SPKR/HP pin, 31, controls the power for the he

DS680F2 45CS42L523/1/136.5.2 Speed ModeConfigures the speed mode of the CODEC in slave mode and sets the appropriate MCLK divide ratio forLRCK and SCL

46 DS680F2CS42L523/1/136.5.6 MCLK Divide By 2Divides the input MCLK by 2 prior to all internal circuitry. Note: In slave mode, this bit is ignored whe

DS680F2 47CS42L523/1/136.6.5 DAC Interface Format Configures the digital interface format for data on SDIN. Note: Select the audio word length for Rig

48 DS680F2CS42L523/1/136.7.3 Tri-State Serial Port InterfaceDetermines the state of the serial port drivers. Notes:1. Slave/Master Mode is determined

DS680F2 49CS42L523/1/136.8.2 PGA Input MappingSelects one or sums/mixes the analog input signal into the PGA. Each bit of the PGAx_SEL[5:1] wordcorres

DS680F2 5CS42L523/1/136.12 Playback Control 1 (Address 0Dh) ...

50 DS680F2CS42L523/1/136.10 ADC HPF Corner Frequency (Address 0Bh)6.10.1 HPF x Corner FrequencySets the corner frequency (-3 dB point) for the interna

DS680F2 51CS42L523/1/136.11.4 Invert ADC Signal PolarityConfigures the polarity of the ADC signal. 6.11.5 ADC MuteConfigures a digital mute on ADC cha

52 DS680F2CS42L523/1/136.12.3 Invert PCM Signal PolarityConfigures the polarity of the digital input signal. 6.12.4 Master Playback MuteConfigures a d

DS680F2 53CS42L523/1/13Using this bit before the relevant circuitry begins normal operation could cause the change to take effect immediately, ignorin

54 DS680F2CS42L523/1/136.14 Playback Control 2 (Address 0Fh)6.14.1 Headphone MuteConfigures a digital mute on headphone channel x. 6.14.2 Speaker Mute

DS680F2 55CS42L523/1/136.15 MICx Amp Control:MIC A (Address 10h) and MIC B (Address 11h)6.15.1 MIC x SelectSelects one of two single-ended MIC inputs

56 DS680F2CS42L523/1/136.16.2 ALCx Zero Cross DisableConfigures an override of the analog zero cross setting. 6.16.3 PGAx VolumeSets the volume/gain

DS680F2 57CS42L523/1/136.17 Passthrough x Volume: PASSAVOL (Address 14h) and PASSBVOL (Address 15h) 6.17.1 Passthrough x Volume Sets the volume/gai

58 DS680F2CS42L523/1/136.19 ADCx Mixer Volume: ADCA (Address 18h) and ADCB (Address 19h)6.19.1 ADC Mixer Channel x MuteConfigures a digital mute on th

DS680F2 59CS42L523/1/136.21 Beep Frequency and On Time (Address 1Ch)6.21.1 Beep Frequency Sets the frequency of the beep signal. Notes:1. This setting

6 DS680F2CS42L523/1/136.25.1 Master Volume Control ...

60 DS680F2CS42L523/1/136.21.2 Beep On TimeSets the on duration of the beep signal.Notes:1. This setting must not change when BEEP is enabled.2. Beep o

DS680F2 61CS42L523/1/136.22.2 Beep Volume Sets the volume of the beep signal.Note: This setting must not change when BEEP is enabled.6.23 Beep and Ton

62 DS680F2CS42L523/1/136.23.3 Treble Corner Frequency Sets the corner frequency (-3 dB point) for the treble shelving filter.6.23.4 Bass Corner Freque

DS680F2 63CS42L523/1/136.24.2 Bass Gain Sets the gain of the bass shelving filter. 6.25 Master Volume Control: MSTA (Address 20h) and MSTB (Address 2

64 DS680F2CS42L523/1/136.27 Speaker Volume Control: SPKA (Address 24h) and SPKB (Address 25h)6.27.1 Speaker Volume Control Sets the volume of the sign

DS680F2 65CS42L523/1/136.29 Limiter Control 1, Min/Max Thresholds (Address 27h)6.29.1 Limiter Maximum Threshold Sets the maximum level, below full sca

66 DS680F2CS42L523/1/136.29.4 Limiter Zero Cross DisableConfigures an override of the digital zero-cross setting. 6.30 Limiter Control 2, Release Rat

DS680F2 67CS42L523/1/136.31 Limiter Attack Rate (Address 29h)6.31.1 Limiter Attack Rate Sets the rate at which the limiter applies digital attenuation

68 DS680F2CS42L523/1/136.33 ALC Release Rate (Address 2Bh)6.33.1 ALC Release RateSets the rate at which the ALC releases the analog and/or digital att

DS680F2 69CS42L523/1/136.34.2 ALC Minimum ThresholdSets the minimum level at which to disengage the ALC’s attenuation or amplify the input signal at t

DS680F2 7CS42L523/1/139.1 Power Supply and Grounding ...

70 DS680F2CS42L523/1/136.35.3 Noise Gate Threshold and BoostTHRESH sets the threshold level of the noise gate. Input signals below the threshold level

DS680F2 71CS42L523/1/136.36.2 DSP Engine Overflow (Read Only)Indicates the over-range status in the DSP data path. 6.36.3 PCMx Overflow (Read Only)In

72 DS680F2CS42L523/1/136.37.3 VP ReferenceSets the desired VP reference used for battery compensation. 6.38 VP Battery Level (Address 30h) (Read Only)

DS680F2 73CS42L523/1/136.39.2 SPKR/HP Pin Status (Read Only)Indicates the status of the SPKR/HP pin. 6.40 Charge Pump Frequency (Address 34h)6.40.1 C

74 DS680F2CS42L523/1/137. ANALOG PERFORMANCE PLOTS7.1 Headphone THD+N versus Output Power PlotsTest conditions (unless otherwise specified): Input tes

DS680F2 75CS42L523/1/13 G = 0.6047G = 0.7099G = 0.8399G = 1.0000G = 1.1430Legend-100-20-95-90-85-80-75-70-65-60-55-50-45-40-35-30dBr A0 60m6m 12m 1

76 DS680F2CS42L523/1/138. EXAMPLE SYSTEM CLOCK FREQUENCIES *The”MCLKDIV2” bit must be enabled.8.1 Auto Detect Enabled 8.2 Auto Detect Disabled S

DS680F2 77CS42L523/1/139. PCB LAYOUT CONSIDERATIONS9.1 Power Supply and GroundingAs with any high-resolution converter, the CS42L52 requires careful a

78 DS680F2CS42L523/1/1310.ADC AND DAC DIGITAL FILTERS Figure 26. ADC Passband Ripple Figure 27. ADC Stopband RejectionFigure 28. ADC Transition Ban

DS680F2 79CS42L523/1/1311.PARAMETER DEFINITIONSDynamic RangeThe ratio of the rms value of the signal to the rms sum of all other spectral components o

8 DS680F2CS42L523/1/131. PIN DESCRIPTIONS Pin Name # Pin DescriptionSDA 1 Serial Control Data (Input/Output) - SDA is a data I/O in I²C Mod

80 DS680F2CS42L523/1/1312.PACKAGE DIMENSIONS1. Dimensioning and tolerance per ASME Y 14.5M-1995.2. Dimensioning lead width applies to the plated termi

DS680F2 81CS42L523/1/1313.ORDERING INFORMATION14.REFERENCES1. Philips Semiconductor, The I²C-Bus Specification: Version 2.1, January 2000.http://www.s

82 DS680F2CS42L523/1/13Contacting Cirrus Logic SupportFor all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find on

DS680F2 9CS42L523/1/13AGND 17 Analog Ground (Input) - Ground reference for the internal analog section.FILT+ 18Positive Voltage Reference (Output) - P