Cirrus-logic CS42516 Uživatelský manuál stáhnout pdf (Strana 79)

DS583F2 79

CS42516

10.1.2 Jitter Attenuation

Figures 28 and 29 show the jitter-attenuation characteristics for the 32-192 kHz sample rate range when

used with the external PLL component values and locking modes as specified in Table 21.

The AES3 and IEC60958-4 specifications do not have allowances for locking to sample rates less than

32 kHz or for locking to the SAI_LRCK input. These specifications state a maximum of 2 dB jitter gain or

peaking.

Figure 28. Jitter-Attenuation Characteristics of PLL - Configurations 1 & 2

Figure 29. Jitter-Attenuation Characteristics of PLL - Configuration 3

1 2 ... 74 75 76 77 78 79 80 81 82 83 84 ... 91 92

Features 1
General Description 1
TABLE OF CONTENTS 2
LIST OF FIGURES 4
LIST OF TABLES 5
ABSOLUTE MAXIMUM RATINGS 6
ANALOG INPUT CHARACTERISTICS 7
ANALOG OUTPUT CHARACTERISTICS 9
SWITCHING CHARACTERISTICS 11
FORMAT 13
DC ELECTRICAL CHARACTERISTICS 14
A (Note 28)Serial Port 15
2. PIN DESCRIPTIONS 16
DS583F2 17 17
18 DS583F2 18
DS583F2 19 19
4. APPLICATIONS 20
4.3 Analog Outputs 21
4.3.2 Interpolation Filter 21
4.3.4 ATAPI Specification 22
4.5 Clock Generation 24
Clock Generation 24
4.5.2 OMCK System Clock Mode 25
4.5.3 Master Mode 25
4.5.4 Slave Mode 25
4.6 Digital Interfaces 26
DS583F2 29 29
Left Channel Right Channel 30
CX_SDOUT 30
SAI_SDOUT 30
MSB LSB MSB LSB 31
4.6.4.1 OLM Config #1 32
4.6.4.2 OLM Config #2 33
4.6.4.3 OLM Config #3 34
4.6.4.4 OLM Config #4 35
4.6.4.5 OLM Config #5 36
4.7.1 SPI Mode 37
4.7.2 I²C Mode 38
4.8 Interrupts 39
4.9 Reset and Power-Up 39
5. REGISTER QUICK REFERENCE 41
42 DS583F2 42
Addr Function 7 6 5 4 3 2 1 0 42
DS583F2 43 43
44 DS583F2 44
6. REGISTER DESCRIPTION 45
76543210 46
Table 5. DAC De-Emphasis 48
Table 6. Receiver De-Emphasis 48
Table 8. ADC One-Line Mode 49
Table 9. DAC One-Line Mode 49
Table 16. ATAPI Decode 60
7. PARAMETER DEFINITIONS 72
8.1 ADC Input Filter 73
8.2 DAC Output Filter 73
9.2.1.1 One-Byte Mode 75
9.2.1.2 Two-Byte Mode 75
9.3.1.1 Format Detection 76
10.APPENDIX C: PLL FILTER 77
10.1.2 Jitter Attenuation 79
10.1.3 Capacitor Selection 80
10.1.4 Circuit Board Layout 81
COMPONENTS 82
DS583F2 83 83
84 DS583F2 84
84
DS583F2 85 85
86 DS583F2 86
DS583F2 87 87
88 DS583F2 88
14.PACKAGE DIMENSIONS 89
THERMAL CHARACTERISTICS 89
64L LQFP PACKAGE DRAWING 89
15.ORDERING INFORMATION 90
16.REFERENCES 90
17.REVISION HISTORY 91
92 DS583F2 92

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